Motorola MPC533 Reference Manual page 616

QSMCM Pin Control Registers
MSB 1
0
Field —
SRESET
Addr
Figure 15-5. QSM2 Dual SCI Interrupt Level Register (QDSCI_IL)
Bits Name
0:2 —
3:7 ILDSCI
8:15 —
MSB 1
0
Field
SRESET
Addr
Figure 15-6. QSPI_IL — QSPI Interrupt Level Register
Bits Name
0:10 —
11:15 ILQSPI
15.5 QSMCM Pin Control Registers
Table 15-7 lists the three QSMCM pin control registers.
15-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
ILDSCI
0000_0000_0000_0000
Table 15-5. QDSCI_IL Bit Descriptions
Reserved
Interrupt level of Dual SCIs
00000lowest interrupt level request (level 0)
11111 highest interrupt level request (level 31)
Reserved
2 3 4 5
—
0000_0000_0000_0000
Table 15-6. QSPI_IL Bit Descriptions
Reserved
Interrupt level of SPI
00000lowest interrupt level request (level 0)
11111 highest interrupt level request (level 31)
MPC533 Reference Manual
6 7 8 9 10
0x30 5004
Description
6 7 8 9 10
0x30 5006
Description
11 12 13 14 LSB
15
—
11 12 13 14
ILQSPI
MOTOROLA