Motorola MPC533 Reference Manual page 238

Memory Map and Register Definitions
SWE
(SYPCR)
System
Clock
Clock
Disable
FREEZE
6.1.11 Freeze Operation
When the FREEZE line is asserted, the clocks to the software watchdog, the periodic
interrupt timer, the real-time clock, the time base counter, and the decrementer can be
disabled. This is controlled by the associated bits in the control register of each timer. If
programmed to stop during FREEZE assertion, the counters maintain their values while
FREEZE is asserted. The bus monitor remains enabled regardless of this signal.
6.1.12 Low Power Stop Operation
When the processor is set in a low-power mode (doze, sleep, or deep-sleep), the software
watchdog timer is frozen. It remains frozen and maintains its count value until the processor
exits this state and resumes executing instructions.
The periodic interrupt timer, decrementer, and time base are not affected by these
low-power modes. They continue to run at their respective frequencies. These timers are
capable of generating an interrupt to bring the MCU out of these low-power modes.
6.2 Memory Map and Register Definitions
This section provides the MPC533 memory map, and diagrams and bit descriptions of the
system configuration and protection registers.
6-24
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SWSR
Service
Logic
Divide By
2048
MUX
SWP
(SYPCR)
Figure 6-10. SWT Block Diagram
MPC533 Reference Manual
SWTC
Reload
16-bit
SWR/Decrementer
Rollover = 0
Reset
or NMI
Time-out
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