Motorola MPC533 Reference Manual page 913

.
Table 21-16. Debug Instructions / Data Shifted into Development Port Shift Register
Start Mode Control
1 0 0
1 0 1
1 1 0
1 1 1
1 1 1
1
Refer to Table 21-13
Data values in the last two functions other than those specified are reserved.
All transmissions from the debug port on DSDO begin with a "0" or "ready" bit. This
indicates that the CPU is trying to read an instruction or data from the port. The external
development tool must wait until it sees DSDO go low to begin sending the next
transmission.
The control bit differentiates between instructions and data and allows the development
port to detect that an instruction was entered when the CPU was expecting data and vice
versa. If this occurs a sequence error indication is shifted out in the next serial transmission.
The trap enable function allows the development tool to transfer data to the trap enable
control register.
The debug port command function allows the development tool to either negate breakpoint
requests, reset the processor, activate or deactivate the fast down load procedure.
The NOP function provides a null operation for use when there is data or a response to be
shifted out of the data register and the appropriate next instruction or command will be
determined by the value of the response or data shifted out.
21.4.6.10 Serial Data Out of Development Port
The encoding of data shifted out of the development port shift register in debug mode
(through the DSDO pin) is the same as for trap enable mode and is shown in Table 21-15.
Valid data encoding is used when data has been transferred from the CPU to the
development port shift register. This is the result of an instruction to move the contents of
a general purpose register to the debug port data register (DPDR). The valid data encoding
has the highest priority of all status outputs and will be reported even if an interrupt occurs
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Instruction / Data (32 Bits)
Bits 0:6
CPU Instruction
CPU Data
1
Trap enable
0011111
0
Chapter 21. Development Support
Bits 7:31
Does not exist
Does not exist
Does not exist
Development Port
Function
Transfer Instruction
to CPU
Transfer Data
to CPU
Transfer data to
Trap Enable
Control Register
Negate breakpoint requests
to the CPU.
NOP
21-43