Memory Bus Controller Considerations - Intel 82496 CACHE CONTROLLER User Manual

CHAPTER 5
HARDWARE INTERFACE
5.1. MEMORY BUS CONTROLLER CONSIDERATIONS
This section explains the functions of a memory bus controller (MBC) for the Pentium
processor CPU-Cache Chip Set. The MBC provides the 82496 Cache Controller/82491 Cache
SRAM's interface to the system memory bus and to any other bus masters. The MBC serves
four primary functions: cycle control, snooping, data control and synchronization.
The 82496 Cache Controller begins each memory bus cycle by signaling the MBC, which then
arbitrates, acquires the bus, and begins the cycle. Once a cycle is in progress on the bus, the
MBC determines if any other cache in the system contains modified data of the line in progress
by signalling these caches to snoop. If another cache signals that it contains modified data, the
MBC permits that cache to write out the modified data before it completes the cycle. Once
transfers have been completed, the MBC ends the cycle.
When a 82496 Cache Controller/82491 Cache SRAM is not the bus master, the MBC handles
snoops from other 82496 Cache Controller/82491 Cache SRAMs or bus masters. If such a
snoop is hit to a modified line, the MBC writes the modified data to memory.
The MBC controls data transfers using the BRDY# signal to the CPU for I/O and memory read
cycles. The MBC also decodes all memory bus cycles, determines their length and
cacheability, and controls them appropriately. Because the CPU core may be running at a
different speed than the memory bus, the MBC provides proper handshaking and
synchronization. Figure 5-1 shows an MBC block diagram.
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5-1