Intel 82496 CACHE CONTROLLER User Manual page 279

HARDWARE INTERFACE
5.2.2.95.
MISTB
MISTB Memory Bus Input Strobe
Strobes data into the 82496 Cache Controller/82491 Cache SRAM.
Input to 82491 Cache SRAM (pin 22)
Asynchronous
Signal Description
MISTB is an input to the 82491 Cache SRAM that cause the 82491 Cache SRAM to input data
through its memory data bus inputs on rising and falling edges. MISTB is used with MSEL#
active to advance the memory burst address counter of the memory buffer in use. As a result,
new data is latched from the memory bus into the 82491 Cache SRAM memory cycle buffer.
MISTB is used in strobed memory bus mode. In clocked memory bus mode, MISTB is the
MBRDY# input.
When Sampled
MISTB is always sampled by the 82491 Cache SRAM. MISTB must meet proper strobed
mode active and inactive times.
Relation to Other Signals
Pin Symbol Relation to Other Signals
MBRDY# MISTB shares a pin with MBRDY#.
MSEL# MISTB is qualified by the MSEL# input. When MSEL# is active, MISTB advances
the memory burst counter for the memory buffer in use to input data through the
memory data bus pins.
MSTBM MSTBM determines whether the 82491 Cache SRAM operates in the strobed
memory bus mode or in clocked memory bus mode.
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