Pentium Processor Cpu-Cache Chip Set Detailed Pin Descriptions - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2. Pentium Processor CPU-Cache Chip Set Detailed Pin
Descriptions
5.2.2.1. A[31 :3)1 A[15:0)
A[31:3] Pentium processor Address bits
A[15:0] 82491 Cache SRAM Address bits
A[31 :3] are Pentium processor Address pins and A[15:0] are 82491 Cache SRAM
Address Pins.
Input/Output Pentium processor signals (pins: V19, W05, V20, VOG, V21, T09,
U19, U08, U20, U09, U21, U10, T10, U11, T11, U12, T12, U13, T13, U14 T14,
U15, T15,U16, T16, U17, U18,W19, T17)
Input 82491 Cache SRAM signals (pins: 82, 81, 80, 79, 78, 77, 76, 75, 73, 71, 70,
69, 68, 67, 66, 65)
Synchronous to ClK
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of the CPU A[31:3]
signals.
82491 Cache SRAM address pins, A[15:1], are connected to CPU address pins A[17:3], and
82491 Cache SRAM address pin AO is always connected to VSS. The Pentium processor
Address pins, A[31:3], are connected to 82496 Cache Controller address pins CFA[6:0],
SET[1O:0], and TAG[11:0]. The specific address pin connections are configuration dependent.
Refer to the Initialization and Configuration chapter for additional details.
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