Intel 82496 CACHE CONTROLLER User Manual page 350

MEMORY BUS FUNCTIONAL DESCRIPTION
perfonned on the CPU bus, in order to guarantee that the replaced data is also removed from
the CPU internal cache, thus maintaining the inclusion property. Note that this example shows
a line ratio of 2 82496 Cache Controller cache lines to 1 Pentium processor cache line.
In clock 1, the CPU issues an ADS# of a read cycle (cycle A). The 82496 Cache Controller
looks-up the cache directory (TAGRAM) and finds the CPU request to be a cache miss. It then
asserts CADS# (also CDTS#) and associated cycle control signals to the MBC (CW/R#,
CM/lO#, CD/C#, CCACHE#, RDYSRC, MCACHE#), in order to schedule the cache line-fill
execution. MCACHE# is active, indicating that the read miss is potentially cacheable by the
82496 Cache Controller (PCD is also inactive in clock 1). RDYSRC is active (high), indicating
that the MBC will supply BRDYs to the CPU.
The 82496 Cache Controller will prepare the 82491 Cache SRAM for the cache line-fill cycle,
by asserting the MCYC#, WAY, and BUS# signals. MCYC# indicates to the 82491 Cache
SRAM that this cycle involves the memory bus. The 82491 Cache SRAM samples and latches
WAY during MCYC# activation. BUS# indicates the 82491 Cache SRAM whould switch the
data source from the ARRAY to the memory-cycle buffer. .
Since the cache directory look-up indicates that a line is going to be replaced, AHOLD is
driven active as a preparation for the CPU back invalidation (clock 3). The CPU address lines
float in clock 4. Thus, the 82496 Cache Controller starts driving the first line address to be
invalidated in clock 6, so it is valid with the setup time to clock 6.
The MBC arbitrates for the memory bus and returns BGT# (clock 4), meaning that the MBC
accepts ownership of the memory bus to complete the current cycle from the 82496 Cache
Controller.
When the memory bus has detennined the cache ability attribute of the cycle, it drives the
MKEN# signal accordingly. At this point the MBC drives the KWEND# signal, indicating the
end of the cacheability window. The 82496 Cache Controller samples MKEN# during
KWEND# (clock 6) and realizes that the cycle in progress is cacheable. This detennination
triggers the start of the back-invalidation (the 82496 Cache Controller waits for the
cacheability detennination, in order to avoid unnecessary back-invalidations, in case the line
happens to be non-cacheable). With this detennination, the 82496 Cache Controller also
activates MAWEA# to infonn the 82491 Cache SRAM to deposit the memory-cycle buffer
content into the ARRAY upon CRDY# (clock 15). The actual physical write to the ARRAY
takes place during clock 16.
In clocks 6 and 8, the 82496 Cache Controller drives EADS# and INV. INV indicates the CPU
to invalidate the line if it hits its internal cache directory (line address is sampled by the
Pentium processor during EADS#). After completing the back-invalidation, the AHOLD
signal is deactivated (clock 9) and the CPU drives the address bus with the new ADS#
(clock 10).
When the snoop window ends on the memory bus, the MBC activates the SWEND# signal.
The 82496 Cache Controller samples MWB/WT# during SWEND# (clock 8) and updates the
cache directory according to the consistency protocol. The closure of the snoop window also
enables the MBC to start providing the CPU with data that has been collected in the 82491
Cache SRAM memory-cycle buffer. The MBC supplies BRDYs to the CPU via BRDY# signal
(clocks 8, 10, 12, and 14). BRDY# is an input to the 82496 Cache Controller needed to track
the burst continuation. -
The 82496 Cache Controller deactivates BLEC# (clock 2) immediately after the ADS# in order
to keep the byte enable infonnation latched in the external latch. BLEC# remains inactive until
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