Integrated System Memory Dram Controller; Accelerated Graphics Port (Agp) Interface; Packaging/Power - Intel 855PM Design Manual

System Overview
Supports 32-bit AGTL+ bus addressing (no support for 36-bit address extension)
Supports Uni-processor (UP) systems
400 MT/s FSB support (100 MHz)
2X Address, 4X Data
8 deep In-Order Queue
2.3.2.

Integrated System Memory DRAM Controller

Supports up to two double-sided SO-DIMMs (four rows populated) with unbuffered
PC1600/PC2100/2700 DDR-SDRAM (with or without ECC)
Supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb technologies for x8 and x16 width devices
Maximum of 2 GB of system memory by using 512-Mb stacked memory technology devices
Supports 200 MHz, 266 MHz and 33MHz DDR devices
64-bit data interface (72-bit with ECC)
PC1600/2100 system memory interface
Supports up to 16 simultaneous open pages
Support for SO-DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power
management support via self refresh mode using CKE
2.3.3.

Accelerated Graphics Port (AGP) Interface

Supports AGP 2.0 data transfers
Supports a single AGP (1X/2X/4X) device (either via a connector or on the motherboard)
Only supports 1.5-V VDDQ for AGP electricals
PCI semantic (FRAME# initiated) accesses to DRAM are snooped
AGP semantic (PIPE# and SBA) traffic to DRAM is not snooped on the FSB and is therefore not
coherent with the CPU caches
High priority access support
Delayed transaction support for AGP reads that cannot be serviced immediately
AGP Busy/Stop Protocol support
Support for D3 Hot and Cold Device states
AGP Clamping and Sense Amp control
2.3.4.

Packaging/Power

593-pin, Micro-FCBGA package (37.5 mm x 37.5 mm)
V
CC-MCH
26
(1.2 V); VCCSM (2.5 V); 1.5 V; VCCGA, VCCHA, & VCC1_8 (1.8 V); V
®
Intel 855PM Chipset Platform Design Guide
R
(1.05 V)
CCP