Configuration Of Snoop Mode; Strong/Weak Write Ordering; Description - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
MBC snooping begins when the snoop strobe (SNPSTB#) signal is asserted. Subsequently, the
82496 Cache Controller samples other snoop information (e.g. the snoop address) and begins a
snoop cycle. The snooping mode determines how the 82496 Cache Controller samples
SNPSTB# and other snoop information.
In Synchronous Snoop Mode, SNPSTB# and other snoop indicators are sampled with the
rising edge of CLK. As a result, the 82496 Cache Controller can begin a snoop without
synchronization and provide quick responses.
In Clocked (Asynchronous) Snoop Mode, SNPSTB# and other snoop indicators are sampled
with the rising edge of snoop clock (SNPCLK), which the MBC can provide at any desired
frequency (less than or the same as CPU CLK). The 82496 Cache Controller synchronizes
snoop information internally before the snoop begins.
In Strobed Snoop Mode, all snoop information is sampled with the falling edge of SNPSTB#.
The 82496 Cache Controller synchronizes snoop information internally before the snoop
begins.
4.3.2.1. CONFIGURATION OF SNOOP MODE
The snoop mode is determined at reset using the SNPCLK [SNPMD] pin. If this pin is tied
LOW, Synchronous Snooping Mode is selected. If tied HIGH, Strobed Snooping Mode is
selected. To select Clocked Snooping Mode, the snoop clock source must be connected to the
SNPCLK pin. The 82496 Cache Controller will automatically detect the clock and enter
Clocked Snooping Mode.
4.3.3. Strong/Weak Write Ordering
4.3.3.1. DESCRIPTION
A system which maintains strong write ordering preserves the sequential ordering of memory
write accesses as they are performed. In processors or systems which contain write buffers and
utilize caching, the order of memory accesses can sometimes fall out of program order. When
the 82496 Cache Controller is configured to be strongly write ordered, it prevents the chip set
from writing data to the bus in any order other than that in which it was received from the
CPU.
A weakly write ordered system can provide greater system design flexibility and slightly
higher performance. When the 82496 Cache Controller is configured to be weakly write
ordered, it will always drive the EWBE# signal active to the CPU. This allows the Pentium
processor to continue issuing writes to 'E' or 'M' in the CPU data cache.
Strongly ordered systems require that instruction execution order be limited to program order.
Increasing the system performance can, therefore, be difficult. A benefit in strongly ordered
systems is that software compatibility is guaranteed. Weakly ordered systems, on the other
hand, completely remove the restrictions on the order of memory accesses; therefore, there
may be software compatibility consequences. When choosing a 82496 Cache Controller
memory write ordering mode, system software compatibility must be maintained.
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