Mdata[7:0] - Intel 82496 CACHE CONTROLLER User Manual

i
ntel
®
HARDWARE INTERFACE
5.2.2.89. MDATA[7:0]
MDATA[7:0] Memory Bus Data Pins
Chip Set memory data bus.
Input/Output of 82491 Cache SRAM (pins 4, 8, 12, 16, 6, 10, 14, 18)
Synchronous to ClK, MClK, MOClK or strobed (MISTB/MOSTB)
Signal Description
MDATA[7:0] comprise the memory data bus of the 82496 Cache Controller/82491 Cache
SRAM cache. Depending on the cache configuration, only half of these pins may be used. The
pins are directly controlled by the MDOE# input. When MDOE# is inactive, these pins are tri-
stated and may be used as inputs.
For write cycles, the 82496 Cache Controller asserts CDTS# to indicate that data is available at
the memory bus data pins or in its buffer. In clocked memory bus mode, data is output with a
valid delay from MCLK or MOCLK, and is changed with respect to MEOC# or MBRDY#. In
strobed memory bus mode, data is output using MOSTB.
For read cycles, data read from the memory bus into the 82491 Cache SRAMs using
MBRDY# (clocked memory bus mode) or MISTB (strobed memory bus mode).
For cache configurations which only require 4 MDATA pins, bits 3-0 are used. Unused
MDATA[7:4] pins MUST be tied either to VSS or to VCC through resistors.
When Sampled/Driven
When the 82496 Cache Controller initiates a write cycle, the write data is written to the
appropriate memory buffer and CDTS# is asserted. If MDOE# is active, the first piece of write
data is available at the memory bus data pins with some delay from the CPU CLK edge in
which CDTS# is asserted. In clocked mode, subsequent pieces of write data are output with
some delay from MCLK or MOCLK (mode dependent) from the edge that MBRDY# is
sampled active. In strobed mode, subsequent data is output with MOSTB assertion. MEOC#
switches memory cycle buffers and outputs the last piece of data if used in place of the last
MBRDY# or MOSTB.
For read cycles, the 82496 Cache Controller asserts CDTS# the CLK before the CPU data path
is available for read data. This means that the memory data bus is available before CDTS# is
asserted. MDOE# must be inactive for the 82491 Cache SRAM to read data. In clocked
memory bus mode, read data is clocked into the 82491 Cache SRAM cache by asserting
MBRDY# on MCLK edges. In strobed mode, data is read by MISTB. Data that is read into the
82491 Cache SRAM's memory data pins must meet proper set-up and hold times. MEOC#
switches memory cycle buffers and latches the last piece of data if used in place of the last
MBRDY# or MISTB.
Data at the data inputs need not follow set-up and hold times to MCLK edges that sample
MBRDY# inactive.
I
5-145