CONTENTS
Figure
7-13.
7-14.
7-15.
7-16.
7-17.
8-1.
8-2.
8-3.
8-4.
9-1.
9-2.
9-3.
10-1.
11-1.
11-2.
11-3.
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
1-8.
1-9.
1-10.
1-11.
1-12.
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
2-1.
2-2.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
xiv
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Valid Delay Timings from Strobes ................................... : ....................................... 7-45
Test Timings ........................................................................................................... 7-46
Test Reset Timings ................................................................................................. 7-46
Active/Inactive Timings ........................................................................................... 7-47
Overshoot/Undershoot and Ringback Guidelines ................................................... 7-49
First Order Input Buffer ............................................................................................. 8-1
First Order Output Buffer .......................................................................................... 8-1
Input Diode Model ..................................................................................................... 8-7
Complete Input Model Including Diode ..................................................................... 8-7
Pentium™ Processor Mechanical Specifications ...................................................... 9-3
82496 Cache Controller Mechanical Specifications .................................................. 9-5
82491 Cache SRAM Mechanical Specifications ....................................................... 9-6
Technique For Measuring Tcase ............................................................................ 10-1
Boundary Scan Register Structure of a Component.. ............................................. 11-5
Device
10
Register .................................................................................................. 11-5
TAP Controller State Diagram ................................................................................ 11-9
Tables
Page
82496 Cache Controller Pin Cross Reference by Pin Name .................................... 1-9
82491 Cache SRAM Pin Cross Reference by Pin Name ........................................ 1-12
82496 Cache Controller/MBC Interface Signals ..................................................... 1-15
82491 Cache SRAM/MBC Interface Signals ........................................................... 1-15
82496 Cache Controller/82491 Cache SRAM Interface Signals ............................ 1-16
Pin States During RESET ....................................................................................... 1-39
Pentium™ Processor Signals Accessible by the MBC .............................................. 2-7
SYNC Cycles .......................................................................................................... 3-16
FLUSH Cycles ........................................................................................................ 3-17
I