Intel 82496 CACHE CONTROLLER User Manual page 265

Volume 2: 82496 cache controller and 82491 cache sram data book
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HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS#
Address and cycle specification signals (Le., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KLOCK#, MAP, MBT[3:0], MCACHE#,
MCFA, MSET, MTAG, NENE#, PALLC#, RDYSRC, and SMLN#) are valid with
CADS#.
5-140
I

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