Read Cycles; Read Hit Cycles - Intel 82496 CACHE CONTROLLER User Manual

CHAPTER 6
MEMORY BUS FUNCTIONAL DESCRIPTION
The 82496 Cache Controller/82491 Cache SRAM core supports a wide variety of bus transfers
to meet the needs of high performance systems. Bus transfers can be single cycle or mUltiple
cycle, cacheable or non-cacheable, 64- or 128-bit (memory bus width), and locked. Depending
on the configuration, multiple cycle transfers may be either 4 or 8 transfer cycles. To support
multiprocessing systems there are cache back-invalidation, inquire, snooping, read for
ownership, cache to cache transfers, and locked cycles.
This chapter begins with read cycles, both cacheable and non-cacheable. It moves on to write
cycles, cacheable and non-cacheable. Snooping, locked, and I/O cycles are also represented by
examples in this chapter. .
The cycles shown in this chapter are examples of various types of Pentium processor CPU-
Cache Chip Set cycles. The purpose of these examples is to show signal relationships, and are
not necessarily best case scenarios. Sample strobe mode inputs MISTB and MOSTB are
indicated in the figures in this chapter for system designers implementing strobed memory bus
mode.
6.1. READ CYCLES
6.1.1. Read Hit Cycles
Read Hit cycles are executed completely within the Pentium processor CPU-Cache Chip Set,
and will not be seen by the MBC.
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