Write Cycles - Intel 82496 CACHE CONTROLLER User Manual

MEMORY BUS FUNCTIONAL DESCRIPTION
in the external latch. Upon receiving CNA# from the MBC (clock 4), BLEC# is activated
again. This enables the sampling of a new cycle. (In case the MBC does not activate CNA#,
BLEC# will be activated again only after CRDY#). Sampling the CNA# active causes the
82496 Cache Controller to drive the next read miss pending cycle (clock 6).
When the MBC drives BRDY#s to the CPU, the maximum level of pipelining is 1 since the
82496 Cache Controller has to sample the last BRDY# of the current CPU cycle in order to
issue another NA#. NA# activation for the second read miss (cycle B) is delayed from clock 5
(blind NA#) to clock 7 (after sampling active BLAST#.BRDY#). This behavior of the NA# is
also shown in the last cycle (D).
6.2. WRITE CYCLES
6.2.1. Write Hit to [E] or [M] State Cycles
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Figure 6-5. Write Hits to [E] or [M] State Cycles
Figure 6-5 illustrates a sequence of Pentium processor memory write cycles that hit 82496
Cache Controller entries marked in the [E] or [M] states. Such cycles are served by the 82496
Cache Controller by directly writing to the 82491 Cache SRAM ARRAY, without any
memory bus activity. Note that the Pentium processor does not pipeline write-back cycles into
previous CPU bus cycles, and will not pipeline a following CPU bus cycle into a Pentium
processor data cache write-back cycle.
In clock 1, the first CPU write cycle (A) starts. The 82496 Cache Controller looks-up the cache
directory (T AGRAM) and detects a hit to [E] or [M] states in clock 2. WRARR# is activated
by the 82496 Cache Controller in preparation for the ARRAY write, and WAY points to the
way to be written. The 82496 Cache Controller asserts BRDYC# in clock 2 (zero wait-state).
Since the BLAST# is also active in clock 2, the 82491 Cache SRAM executes a write cycle
into the ARRAY in the first half of clock 3.
6-10
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