Kwend - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.70.
KWEND#
KWEND#
Cacheability Window End
Closes the 82496 Cache Controller cacheability window.
Input to 82496 Cache Controller (pin N05)
Synchronous to ClK
Internal Pull-up
Signal Description
KWEND# is a cycle progress input which closes the cacheability window opened with
CADS#, and causes the MKEN# and MRO# cacheability attributes to be sampled.
KWEND# should be asserted by the MBC once the memory address has been decoded and
MKEN# (cacheability) and MRO# (read-only) attributes have been determined.
Resolving KWEND# quickly allows the non-snoopable window between BGT# and SWEND#
to be closed more quickly. KWEND# activation also allows the 82496 Cache Controller to
start allocations and begin replacements.
When Sampled
KWEND# is sampled by the 82496 Cache Controller on the CLK in which BGT# is sampled
active or on the following CLKs. Once KWEND# is sampled active, it is not sampled again
until BGT# of the next cycle.
BGT#, KWEND# and SWEND# may be asserted on the same CLK edge.
KWEND# need only be activated for cycles requiring MKEN# and MRO# to be sampled (i.e.
cacheable read misses and write cycles with potential allocate).
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