Page 1 80C186XL/80C188XL Microprocessor User’s Manual...
Page 2 80C186XL/80C188XL Microprocessor User’s Manual 1995...
Page 3 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Page 4: Table Of Contents
CHAPTER 1 INTRODUCTION HOW TO USE THIS MANUAL... 1-2 RELATED DOCUMENTS ... 1-3 ELECTRONIC SUPPORT SYSTEMS ... 1-4 1.3.1 FaxBack Service ...1-4 1.3.2 Bulletin Board System (BBS) ...1-5 1.3.2.1 How to Find Ap BUILDER Software and Hypertext Documents on the BBS ...1-6 1.3.3 CompuServe Forums ...1-6 1.3.4...
Page 5 CONTENTS INTERRUPTS AND EXCEPTION HANDLING ... 2-39 2.3.1 Interrupt/Exception Processing ...2-39 2.3.1.1 Non-Maskable Interrupts ...2-42 2.3.1.2 Maskable Interrupts ...2-43 2.3.1.3 Exceptions ...2-43 2.3.2 Software Interrupts ...2-45 2.3.3 Interrupt Latency ...2-45 2.3.4 Interrupt Response Time ...2-46 2.3.5 Interrupt and Exception Priority ...2-46 CHAPTER 3 BUS INTERFACE UNIT MULTIPLEXED ADDRESS AND DATA BUS ...
Page 6 CHAPTER 4 PERIPHERAL CONTROL BLOCK PERIPHERAL CONTROL REGISTERS... 4-1 PCB RELOCATION REGISTER... 4-1 RESERVED LOCATIONS ... 4-4 ACCESSING THE PERIPHERAL CONTROL BLOCK ... 4-4 4.4.1 Bus Cycles ...4-4 4.4.2 READY Signals and Wait States ...4-4 4.4.3 F-Bus Operation ...4-5 4.4.3.1 Writing the PCB Relocation Register ...4-6 4.4.3.2 Accessing the Peripheral Control Registers ...4-6...
Page 7 CONTENTS 6.4.5 Memory or I/O Bus Cycle Decoding ...6-17 6.4.6 Programming Considerations ...6-17 CHIP-SELECTS AND BUS HOLD... 6-18 EXAMPLES ... 6-18 6.6.1 Example 1: Typical System Configuration ...6-18 CHAPTER 7 REFRESH CONTROL UNIT THE ROLE OF THE REFRESH CONTROL UNIT... 7-2 REFRESH CONTROL UNIT CAPABILITIES...
Page 8 PROGRAMMING THE INTERRUPT CONTROL UNIT ... 8-11 8.4.1 Interrupt Control Registers ...8-12 8.4.2 Interrupt Request Register ...8-16 8.4.3 Interrupt Mask Register ...8-16 8.4.4 Priority Mask Register ...8-17 8.4.5 In-Service Register ...8-18 8.4.6 Poll and Poll Status Registers ...8-19 8.4.7 End-of-Interrupt (EOI) Register ...8-21 8.4.8 Interrupt Status Register ...8-22 SLAVE MODE ...
Page 9 CONTENTS 10.1.3 DMA Requests ...10-3 10.1.4 External Requests ...10-4 10.1.4.1 Source Synchronization ...10-5 10.1.4.2 Destination Synchronization ...10-5 10.1.5 Internal Requests ...10-6 10.1.5.1 Timer 2-Initiated Transfers ...10-6 10.1.5.2 Unsynchronized Transfers ...10-6 10.1.6 DMA Transfer Counts ...10-7 10.1.7 Termination and Suspension of DMA Transfers ...10-7 10.1.7.1 Termination at Terminal Count ...10-7 10.1.7.2...
Page 10 11.3.1.4 Transcendental Instructions ...11-5 11.3.1.5 Constant Instructions ...11-6 11.3.1.6 Processor Control Instructions ...11-6 11.3.2 80C187 Data Types ...11-7 11.4 MICROPROCESSOR AND COPROCESSOR OPERATION... 11-7 11.4.1 Clocking the 80C187 ...11-10 11.4.2 Processor Bus Cycles Accessing the 80C187 ...11-10 11.4.3 System Design Tips ...11-11 11.4.4 Exception Trapping ...11-13 11.5...
Page 11 CONTENTS Figure Simplified Functional Block Diagram of the 80C186 Family CPU ...2-2 Physical Address Generation ...2-3 General Registers ...2-4 Segment Registers ...2-6 Processor Status Word ...2-9 Segment Locations in Physical Memory...2-10 Currently Addressable Segments...2-11 Logical and Physical Address ...2-12 Dynamic Code Relocation ...2-14 2-10 Stack Operation...2-16 2-11...
Page 12 Figure 3-15 Generating a Normally Not-Ready Bus Signal ...3-16 3-16 Generating a Normally Ready Bus Signal ...3-17 3-17 Normally Not-Ready System Timing ...3-18 3-18 Normally Ready System Timings ...3-19 3-19 Typical Read Bus Cycle ...3-21 3-20 Read-Only Device Interface ...3-22 3-21 Typical Write Bus Cycle...3-23 3-22...
Page 13 CONTENTS Figure 6-11 Wait State and Ready Control Functions ...6-16 6-12 Using Chip-Selects During HOLD ...6-18 6-13 Typical System ...6-19 Refresh Control Unit Block Diagram...7-1 Refresh Control Unit Operation Flow Chart...7-3 Refresh Address Formation...7-4 Suggested DRAM Control Signal Timing Relationships...7-6 Formula for Calculating Refresh Interval for RFTIME Register ...7-7 Refresh Base Address Register ...7-8 Refresh Clock Interval Register...7-9...
Page 14 Figure 10-3 Source-Synchronized Transfers ...10-5 10-4 Destination-Synchronized Transfers ...10-6 10-5 Two-Channel DMA Module ...10-9 10-6 Examples of DMA Priority...10-10 10-7 DMA Source Pointer (High-Order Bits)...10-11 10-8 DMA Source Pointer (Low-Order Bits) ...10-12 10-9 DMA Destination Pointer (High-Order Bits) ...10-13 10-10 DMA Destination Pointer (Low-Order Bits)...10-14 10-11 DMA Control Register...10-15...
Page 15 CONTENTS Table Comparison of 80C186 Modular Core Family Products ...1-2 Related Documents and Software...1-3 Implicit Use of General Registers ...2-5 Logical Address Sources...2-13 Data Transfer Instructions ...2-18 Arithmetic Instructions ...2-20 Arithmetic Interpretation of 8-Bit Numbers ...2-21 Bit Manipulation Instructions ...2-21 String Instructions...2-22 String Instruction Register and Flag Use...2-23 Program Transfer Instructions ...2-25...
Page 16 Table Instruction Format Variables... C-1 Instruction Operands ... C-2 Flag Bit Functions... C-3 Instruction Set ... C-4 Operand Variables ... D-1 Instruction Set Summary ... D-2 Machine Instruction Decoding Guide... D-9 Mnemonic Encoding Matrix (Left Half) ... D-20 Abbreviations for Mnemonic Encoding Matrix ... D-22 TABLES CONTENTS Page...
Page 17 CONTENTS Example Initializing the Power Management Unit for Power-Save Mode ...5-14 Initializing the Chip-Select Unit...6-20 Initializing the Refresh Control Unit ...7-11 Initializing the Interrupt Control Unit for Master Mode ...8-31 Configuring a Real-Time Clock...9-18 Configuring a Square-Wave Generator ...9-21 Configuring a Digital One-Shot...9-22 10-1 Initializing the DMA Unit ...10-23 10-2...
Page 18 Introduction...
Page 20 As technology advanced and turned toward small geometry CMOS processes, it became clear that a new 80186 was needed. In 1987 Intel announced the second generation of the 80186 family: the 80C186/C188. The 80C186 family is pin compatible with the 80186 family, while adding an enhanced feature set.
Page 21: Introduction
INTRODUCTION The 80C186 Modular Core family is the direct result of ten years of Intel development. It offers the designer the peace of mind of a well-established architecture with the benefits of state-of-the- art technology. Table 1-1. Comparison of 80C186 Modular Core Family Products...
Page 22: Related Documents
The following table lists documents and software that are useful in designing systems that incor- porate the 80C186 Modular Core Family. These documents are available through Intel Literature. To order a document, call the number listed for your area in “Product Literature” on page 1-7.
Page 23: Electronic Support Systems
ZCON - Z80 Code Converter ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information. Intel also maintains several forums on CompuServe and offers a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical infor- mation whenever you need it.
Page 24: Bulletin Board System (Bbs)
BBS file listings Microprocessor, PCI, and peripheral catalog Quality and reliability and change notification catalog iAL (Intel Architecture Labs) technology catalog 1.3.2 Bulletin Board System (BBS) The bulletin board system (BBS) lets you download files to your computer. The application BBS has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firm- ware upgrades, application notes and utilities, and quality and reliability data.
Page 25: How To Find Ap Builder Software And Hypertext Documents On The Bbs
BBS. To access the files, complete these steps: Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area number.
Page 26: Product Literature
708-296-9333 44(0)1793-431155 44(0)1793-421333 44(0)1793-421777 81(0)120-47-88-32 TRAINING CLASSES In the U.S. and Canada, you can register for training classes through the Intel customer training center. Classes are held in the U.S. 1-800-234-8806 U.S. and Canada U.S. (from overseas) Europe (U.K.) Germany...
Page 28: Overview Of The 80C186 Family Architecture
Overview of the 80C186 Family Architecture...
Page 30: Architectural Overview
CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086, 8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 80C186 Modular Core maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors, while adding hardware and software performance enhancements.
Page 31: Execution Unit
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE General Registers Temporary Registers Flags Execution Unit (EU) Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU 2.1.1 Execution Unit The Execution Unit executes all instructions, provides data and addresses to the Bus Interface Unit and manipulates the general registers and the Processor Status Word.
Page 32: Bus Interface Unit
The Execution Unit does not connect directly to the system bus. It obtains instructions from a queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Ad- dresses manipulated by the Execution Unit are 16 bits wide.
Page 33: General Registers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit sequentially prefetches instructions from memory. As long as the prefetch queue is partially full, the Execution Unit fetches instructions. 2.1.3 General Registers The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3).
Page 34: Segment Registers
The data registers can be addressed by their upper or lower halves. Each data register can be used interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always access- ed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and log- ic operations.
Page 35: Instruction Pointer
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.5 Instruction Pointer The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer, but it can change, be saved or be restored as a result of program execution.
Page 36: Flags
2.1.6 Flags The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit posts as the result of arithmetic or logical operations. Program branch instructions allow a pro- gram to alter its execution depending on conditions flagged by a prior operation. Different in- structions affect the status flags differently, generally reflecting the following states: •...
Page 37: Memory Segmentation
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.7 Memory Segmentation Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long. Each segment is composed of contiguous memory locations.
Page 38: Processor Status Word
Parity Flag Carry Flag NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 2-5. Processor Status Word OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE...
Page 39: Logical Addresses
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Fully Overlapped Partly Overlapped Contiguous Segment A Segment B 10000H Figure 2-6. Segment Locations in Physical Memory The four segment registers point to four “currently addressable” segments (see Figure 2-7). The currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64 Kbytes for stack and 128 Kbytes for data storage.
Page 40: Currently Addressable Segments
Data: Code: Stack: Extra: Figure 2-7. Currently Addressable Segments The segment register is automatically selected according to the rules in Table 2-2. All information in one segment type generally shares the same logical attributes (e.g., code or data). This leads to programs that are shorter, faster and better structured.
Page 41: Logical And Physical Address
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Physical Address Logical Addresses Figure 2-8. Logical and Physical Address 2-12 Offset (3H) Segment Base Offset (13H) Segment Base 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H...
Page 42: Dynamically Relocatable Code
Table 2-2. Logical Address Sources Type of Memory Reference Instruction Fetch Stack Operation Variable (except following) String Source String Destination BP Used as Base Register Instructions are always fetched from the current code segment. The IP register contains the in- struction’s offset from the beginning of the segment.
Page 43: Dynamic Code Relocation
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before Relocation Code Segment Stack Segment Data Segment Extra Segment Figure 2-9. Dynamic Code Relocation To be dynamically relocatable, a program must not load or alter its segment registers and must not transfer directly to a location outside the current code segment. All program offsets must be relative to the segment registers.
Page 44: 2.1.10 Stack Implementation
0FFFF0H. • Locations 0F8H through 0FFH in I/O space are reserved for communication with other Intel hardware products and must not be used. On the 80C186 core, these addresses are used as I/O ports for the 80C187 numerics processor extension.
Page 45: Stack Operation
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Existing Stack 1062 1060 105E 105B 105A 1058 1056 1054 1052 1050 Stack operation for code sequence 2-16 PUSH AX 1062 1060 105E 105B 105A 1058 1056 1054 1052 1050 PUSH AX POP AX POP BX Figure 2-10.
Page 46: Software Overview
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE SOFTWARE OVERVIEW All 80C186 Modular Core family members execute the same instructions. This includes all the 8086/8088 instructions plus several additions and enhancements (see Appendix A, “80C186 In- struction Set Additions and Extensions”). The following sections describe the instructions by cat- egory and provide a detailed discussion of the operand addressing modes.
Page 47: Data Transfer Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.1 Data Transfer Instructions The instruction set contains 14 data transfer instructions. These instructions move single bytes and words between memory and registers. They also move single bytes and words between the AL or AX register and I/O ports. Table 2-3 lists the four types of data transfer instructions and their functions.
Page 48: Arithmetic Instructions
PUSHF POPF U = Undefined; Value is indeterminate O = Overflow Flag D = Direction Flag I = Interrupt Enable Flag T = Trap Flag S = Sign Flag Z = Zero Flag A = Auxiliary Carry Flag P = Parity Flag C = Carry Flag Figure 2-11.
Page 49: Arithmetic Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-5 shows the interpretations of various bit patterns according to number type. Binary num- bers can be 8 or 16 bits long. Decimal numbers are stored in bytes, two digits per byte for packed decimal and one digit per byte for unpacked decimal.
Page 50: Bit Manipulation Instructions
Table 2-5. Arithmetic Interpretation of 8-Bit Numbers Bit Pattern 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 2.2.1.3 Bit Manipulation Instructions There are three groups of instructions for manipulating bits within bytes and words. These three groups are logical, shifts and rotates.
Page 51: String Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Individual bits in bytes and words can also be rotated. The processor does not discard the bits ro- tated out of an operand. The bits circle back to the other end of the operand. The number of bits to be rotated is taken from the count operand, which can specify either an immediate value or the CL register.
Page 52: Program Transfer Instructions
String instructions automatically update the SI register, the DI register, or both, before processing the next string element. The Direction Flag (DF) determines whether the index registers are auto- incremented (DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or both registers by one for byte strings or by two for word strings.
Page 53 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Unconditional transfer instructions can transfer control either to a target instruction within the current code segment (intrasegment transfer) or to a different code segment (intersegment trans- fer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR.
Page 54: Program Transfer Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-9. Program Transfer Instructions Conditional Transfers JA/JNBE Jump if above/not below nor equal JAE/JNB Jump if above or equal/not below JB/JNAE Jump if below/not above nor equal JBE/JNA Jump if below or equal/not above Jump if carry JE/JZ Jump if equal/zero...
Page 55: Interpretation Of Conditional Transfers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Iteration control instructions can be used to regulate the repetition of software loops. These in- structions use the CX register as a counter. Like the conditional transfers, the iteration control in- structions are self-relative and can transfer only to targets that are within –128 to +127 bytes of themselves.
Page 56: Processor Control Instructions
2.2.1.6 Processor Control Instructions Processor control instructions (see Table 2-11) allow programs to control various CPU functions. Seven of these instructions update flags, four of them are used to synchronize the microprocessor with external events, and the remaining instruction causes the CPU to do nothing. Except for flag operations, processor control instructions do not affect the flags.
Page 57: Memory Addressing Modes
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Immediate operands are constant data contained in an instruction. Immediate data can be either 8 or 16 bits in length. Immediate operands are available directly from the instruction queue and can be accessed quickly. As with a register operand, no bus cycles need to be run to get an imme- diate operand.
Page 58: Memory Address Computation
Single Index Encoded in the Instruction Explicit in the Instruction Assumed Unless Overridden by Prefix Figure 2-12. Memory Address Computation The displacement is an 8- or 16-bit number contained in the instruction. The displacement gen- erally is derived from the position of the operand’s name (a variable or label) in the program. The programmer can modify this value or explicitly specify the displacement.
Page 59: Direct Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The BX or BP register can be specified as the base register for an effective address calculation. Similarly, either the SI or the DI register can be specified as the index register. The displacement value is a constant.
Page 60: Register Indirect Addressing
Opcode Figure 2-14. Register Indirect Addressing Opcode Figure 2-15. Based Addressing Based addressing provides a simple way to address data structures that may be located in different places in memory (see Figure 2-16). A base register can be pointed at the structure. Elements of the structure can then be addressed by their displacements.
Page 61: Accessing A Structure With Based Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Displacement (Rate) Base Register Figure 2-16. Accessing a Structure with Based Addressing With indexed addressing, the effective address is calculated by summing a displacement and the contents of an index register (SI or DI, see Figure 2-17). Indexed addressing is often used to ac- cess elements in an array (see Figure 2-18).
Page 62: Indexed Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M Figure 2-17. Indexed Addressing High Address Array (8) Displacement Array (7) Array (6) Array (5) Index Register Array (4) Array (3) Array (2) Array (1) Array (0) Low Address Figure 2-18. Accessing an Array with Indexed Addressing Displacement Displacement Index Register...
Page 63: Based Index Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Based index addressing generates an effective address that is the sum of a base register, an index register and a displacement (see Figure 2-19). The two address components can be determined at execution time, making this a very flexible addressing mode. Opcode Figure 2-19.
Page 64: Accessing A Stacked Array With Based Index Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address Displacement Base Register (BP) Index Register Low Address Figure 2-20. Accessing a Stacked Array with Based Index Addressing Parm 2 Displacement Parm 1 Old BP Base Register (BP) Old BX Old AX Array (6) Index Register Array (5)
Page 65: I/O Port Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Source EA Destination EA A1025-0A Figure 2-21. String Operand 2.2.2.3 I/O Port Addressing Any memory operand addressing modes can be used to access an I/O port if the port is memory- mapped. String instructions can also be used to transfer data to memory-mapped ports with an appropriate hardware interface.
Page 66: Data Types Used In The 80C186 Modular Core Family
2.2.2.4 Data Types Used in the 80C186 Modular Core Family The 80C186 Modular Core family supports the data types described in Table 2-12 and illustrated in Figure 2-23. In general, individual data elements must fit within defined segment limits. Table 2-12. Supported Data Types Type Integer A signed 8- or 16-bit binary numeric value (signed byte or word).
Page 67: C186 Modular Core Family Supported Data Types
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Signed Byte Sign Bit Magnitude 15 14 Signed Word Sign Bit Magnitude Signed Double Word* Sign Bit Signed Quad Word* Sign Bit Binary Coded Decimal (BCD) BCD Digit n ASCII ASCII Character n Packed BCD Most Significant Digit String...
Page 68: Interrupts And Exception Handling
Each interrupt or exception is given a type number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that in- terrupt types 0–31 are reserved for Intel and should not be used by an application program. OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE...
Page 69: Interrupt Vector Table
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Memory Table Vector Address Entry Definition Type 255 Type 32 Type 31 Type 20 Type 19 - Timer 2 Type 18 - Timer 1 Type 17 - Reserved Type 16 - Numerics Type 15 - INT3 Type 14 - INT2 Type 13 - INT1 Type 12 - INT0...
Page 70 The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This prevents maskable interrupts or single step exceptions from interrupting the processor during the interrupt service routine. The current CS and IP are pushed onto the stack. The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt Vector Table and begins executing from that point.
Page 71: Non-Maskable Interrupts
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Stack Interrupt Vector Table Figure 2-26. Interrupt Sequence 2.3.1.1 Non-Maskable Interrupts The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a catastrophic event such as impending power failure. An NMI cannot be prevented (or masked) by software.
Page 72: Maskable Interrupts
2.3.1.2 Maskable Interrupts Maskable interrupts are the most common way to service external hardware interrupts. Software can globally enable or disable maskable interrupts. This is done by setting or clearing the Inter- rupt Enable bit in the Processor Status Word. The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents them to the core via a single maskable interrupt input.
Page 73 80C188 Modular Core Family members do not support the 80C187 interface and always generate the Escape Opcode Fault. The 80C186XL will generate the Escape Opcode Fault regardless of the state of the Escape Trap bit unless it is in Numerics Mode.
Page 74: Software Interrupts
2.3.2 Software Interrupts A Software Interrupt is caused by executing an “INTn” instruction. The n parameter corresponds to the specific interrupt type to be executed. The interrupt type can be any number between 0 and 255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt (NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in the Interrupt Status register are not altered.
Page 75: Interrupt Response Time
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.4 Interrupt Response Time Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction in the service routine is executed. Interrupt response time is less for interrupts or exceptions which supply their own vector type.
Page 76: Simultaneous Nmi And Exception
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Only the single step exception can occur concurrently with another exception. At most, two ex- ceptions can occur at the same instruction boundary and one of those exceptions must be the sin- gle step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now), only one exception can occur at any given instruction boundary.
Page 77: Simultaneous Nmi And Single Step Interrupts
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruc- tion boundary as a single step, the interrupt vector is taken first, then is followed immediately by the single step vector.
Page 78: Simultaneous Nmi, Single Step And Maskable Interrupt
Interrupt Enable Bit (IE) = 1 Trap Flag (TF) = 1 Divide Timer Interrupt Push PSW, CS, IP Fetch Divide Error Vector Push PSW, CS, IP Fetch NMI Vector Push PSW, CS, IP Fetch Single Step Vector Execute Single Step Service Routine Interrupt Enable Bit (IE) = 0 Trap Flag (TF) = ???
Page 80 Bus Interface Unit...
Page 82: Multiplexed Address And Data Bus
The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass data to and from the execution unit, and pass data to and from the integrated peripheral units. The BIU drives address, data, status and control information to define a bus cycle. The start of a bus cycle presents the address of a memory or I/O location and status information defining the type of bus cycle.
Page 83: Physical Data Bus Models
BUS INTERFACE UNIT Physical Implementation of the Address Space for 8-Bit Systems 1 MByte FFFFF FFFFE A19:0 D7:0 Figure 3-1. Physical Data Bus Models Byte transfers to even addresses transfer information over the lower half of the data bus (see Fig- ure 3-2).
Page 84: Bit Data Bus Byte Transfers
Even Byte Transfer Y + 1 X + 1 A19:1 D15:8 (High) Odd Byte Transfer Y + 1 (X + 1) A19:1 D15:8 (Low) Figure 3-2. 16-Bit Data Bus Byte Transfers BUS INTERFACE UNIT D7:0 (Low) D7:0 (High) A1104-0A...
Page 85: Bit Data Bus Even Word Transfers
BUS INTERFACE UNIT (X + 1) A19:1 D15:8 D7:0 (Low) (Low) A1107-0A Figure 3-3. 16-Bit Data Bus Even Word Transfers During a byte read operation, the BIU floats the entire 16-bit data bus, even though the transfer occurs on only one half of the bus. This action simplifies the decoding requirements for read-only devices (e.g., ROM, EPROM, Flash).
Page 86: Bit Data Bus
(X + 1) A19:1 D15:8 Y + 1 X + 1 A19:1 D15:8 Figure 3-4. 16-Bit Data Bus Odd Word Transfers 3.2.2 8-Bit Data Bus The memory address space on an 8-bit data bus is physically implemented as one bank of 1 Mbyte (see Figure 3-1 on page 3-2).
Page 87: Memory And I/O Interfaces
BUS INTERFACE UNIT For word transfers, the word address defines the first byte transferred. The second byte transfer occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus in- terface. Second Bus Cycle First Bus Cycle (X + 1) A19:0...
Page 88: Bit Bus Memory And I/O Requirements
3.3.1 16-Bit Bus Memory and I/O Requirements A 16-bit bus has certain assumptions that must be met to operate properly. Memory used to store instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction prefetch bus cycles require that both banks be used. The lower bank contains the even bytes of code and the upper bank contains the odd bytes of code.
Page 89: Typical Bus Cycle
BUS INTERFACE UNIT CLKOUT S2:0 AD15:0 RD / WR CLKOUT Figure 3-7. T-State Relation to CLKOUT Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T- states labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pending. Multiple T3 states occur to generate wait states.
Page 90: Biu State Diagram
The address/status phase starts just before T1 and continues through T1. The data phase starts at T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases. Request Pending HOLD Deasserted Asserted Request Pending HOLD Deasserted Halt Bus Cycle No Request Pending HOLD Deasserted...
Page 91: Address/Status Phase
BUS INTERFACE UNIT or TI or TW or TI CLKOUT Address/ Data Phase Status Phase A1113-0A Figure 3-9. T-State and Bus Phases 3.4.1 Address/Status Phase Figure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A bus cycle begins with the transition of ALE and S2:0.
Page 92: Address/Status Phase Signal Relationships
or TI CLKOUT AD15:0 A19:16 Address S2:0 NOTES: 1. T CHLH T CHSV : Clock high to ALE high, S2:0 valid. 2. T CLAV : Clock low to address valid, BHE valid. 3. T AVLL : Address valid to ALE low (address setup to ALE). 4.
Page 93: Demultiplexing Address Information
BUS INTERFACE UNIT Signals From CPU A19:16 S2:0 AD15:8 AD7:0 Figure 3-11. Demultiplexing Address Information Status Bit 3-12 Latched Address Signals LA19:16 LS2:0 LA15:8 LA7:0 Table 3-1. Bus Cycle Types Operation Interrupt Acknowledge I/O Read I/O Write Halt Instruction Prefetch Memory Read Memory Write Idle (passive)
Page 94: Data Phase
3.4.2 Data Phase Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle type that does not have a data phase is a bus halt. During the data phase, the bus transfers infor- mation between the internal units and the memory or peripheral device selected during the ad- dress/status phase.
Page 95: Data Phase Signal Relationships
BUS INTERFACE UNIT CLKOUT RD/ WR AD15:0 Write AD15:0 Read S2:0 NOTES: 1. T CLRL/CLWL, T CLOV : Clock low to valid RD/WR active, write data valid. 2. T CLSH : Clock low to status inactive. 3. T DVCL : Data input valid to clock low. 4.
Page 96: Typical Bus Cycle With Wait States
CLKOUT S2:0 Address A19:16 Address AD15:0 READY Figure 3-13. Typical Bus Cycle with Wait States ARDY Rising CLKOUT Edge SRDY Figure 3-14. ARDY and SRDY Pin Block Diagram Valid Valid Write Data BUS INTERFACE UNIT A1040-0A BUS READY Falling Edge A1041-0A 3-15...
Page 97: Generating A Normally Not-Ready Bus Signal
BUS INTERFACE UNIT A normally not-ready system is one in which ARDY and SRDY remain low at all times except to signal a ready condition. For any bus cycle, only the selected device drives either ready input high to complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to generate a normally not-ready signal.
Page 98: Generating A Normally Ready Bus Signal
CLKOUT Figure 3-16. Generating a Normally Ready Bus Signal The ARDY input has two major timing concerns that can affect whether a normally ready or nor- mally not-ready signal may be required. Two latches capture the state of the ARDY input (see Figure 3-14 on page 3-15).
Page 99: Idle States
BUS INTERFACE UNIT CLKOUT ARDY SRDY In a Normally-Not-Ready system, wait states are inserted until (1 or 2) and 3 are met. 1. T ARYCH : ARDY active to clock high (assumes ARDY remains active until 3). 2. T SRYCL : SRDY active to clock low. 3.
Page 100: Normally Ready System Timings
CLKOUT ARDY In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met. (Assumes SRDY is low.) 1. T ARYCH : ARDY low to clock high 2. T ARYCHL : Clock high to ARDY high (ARDY inactive hold time) CLKOUT ARDY SRDY...
Page 101: Bus Cycles
BUS INTERFACE UNIT An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle con- tinues to float the bus. An idle bus state following a bus write cycle continues to drive the bus. The BIU drives no control strobes active in an idle state except to indicate the start of another bus cycle.
Page 102: Typical Read Bus Cycle
and T define the maximum data access requirements for the memory device. These device parameters must be less than the value calculated in the equation column. An equal to or greater than result indicates that wait states must be inserted into the bus cycle. determines the maximum time the memory device can float its outputs before the next bus cycle begins.
Page 103: Refresh Bus Cycles
BUS INTERFACE UNIT 3.5.1.1 Refresh Bus Cycles A refresh bus cycle operates similarly to a normal read bus cycle except for the following: • For a 16-bit data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the bus is ignored.
Page 104: Typical Write Bus Cycle
CLKOUT S2:0 A19:16 [A15:8] A15:0 [AD7:0] DT/R Figure 3-21. Typical Write Bus Cycle Table 3-4. Write Bus Cycle Types Status Bits Write I/O — Initiated by executing IN, OUT, INS, OUTS instructions or by the DMA Unit. A15:0 select the desired I/O port. A19:16 are driven to zero (see Chapter 10, “Direct Memory Access Unit”).
Page 105: Bit Bus Read/Write Device Interface
BUS INTERFACE UNIT Most memory and peripheral devices latch data on the rising edge of the write strobe. Address, chip-select and data must be valid (set up) prior to the rising edge of WR. T fine the minimum data setup requirements. The value calculated by their respective equations must be greater than the device requirements.
Page 106: Interrupt Acknowledge Bus Cycle
The minimum device data hold time (from WR high) is defined by T must be greater than the minimum device requirements; however, the value can be changed only by decreasing the clock rate. Table 3-5. Write Cycle Critical Timing Parameters Memory Device Parameter Write cycle time...
Page 107: Interrupt Acknowledge Bus Cycle
BUS INTERFACE UNIT CLKOUT S2:0 INTA0 Note INTA1 AD15:0 [AD7:0] LOCK DT/R A19:16 [A15:8] RD, WR NOTE: Vector Type is read from AD7:0 only. INTA occurs during T2 in slave mode. Figure 3-23. Interrupt Acknowledge Bus Cycle 3-26 Note A15:8 are unknown A19:16 are driven low Note A1048-0A...
Page 108: System Design Considerations
Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate both bus cycles in the interrupt acknowledge sequence. Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space.
Page 109: Halt Bus Cycle
BUS INTERFACE UNIT 3.5.4 HALT Bus Cycle Suspending the CPU reduces device power consumption and potentially reduces interrupt latency time. The HLT instruction initiates two events: Suspends the Execution Unit. Instructs the BIU to execute a HALT bus cycle. After executing a HALT bus cycle, the BIU suspends operation until one of the following events occurs: •...
Page 110: Halt Bus Cycle Pin States
CLKOUT S2:0 AD15:0 [AD7:0] [A15:8] A19:16 [RFSH = 1] NOTES: 1. The AD15:0 [AD7:0] bus can be floating, driving a previous write data value, or driving the next instruction prefetch address value. For an 8-bit device, A15:8 drives either the previous bus address value or the next instruction prefetch address value.
Page 111: Temporarily Exiting The Halt Bus State
BUS INTERFACE UNIT 3.5.5 Temporarily Exiting the HALT Bus State A DMA request, refresh request or bus hold request causes the BIU to exit the HALT bus state temporarily. This can occur only when in the Active or Idle power management mode. The BIU returns to the HALT bus state after it completes the desired bus operation.
Page 112: Returning To Halt After A Refresh Bus Cycle
CLKOUT S2:0 AD15:0 Addr [AD7:0] [A15:8] Note 1 A19:16 Note 1 Note 2 RFSH NOTES: 1. Previous bus cycle value. 2. Only occurs for BHE on the first refresh bus cycle after entering HALT. 3. BHE = 1 for 16-bit device, RFSH = 0 for 8-bit device. Figure 3-27.
Page 113: Exiting Halt
BUS INTERFACE UNIT T1 T2 T3 T4 T1 T2 T3 CLKOUT S2:0 Valid Status AD15:0 Addr [AD7:0] [A15:8] Note A19:16 Note Addr Note [RFSH=1] NOTE: Drives previous bus cycle value. Figure 3-28. Returning to HALT After a DMA Bus Cycle 3.5.6 Exiting HALT An NMI or any unmasked INTn interrupt causes the BIU to exit HALT.
Page 114: System Design Alternatives
CLKOUT Note 1 NMI/INTx S2:0 AD15:0 [AD7:0] [A15:8] A19:16 RFSH NOTES: 1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min). 2. Previous bus cycle value. SYSTEM DESIGN ALTERNATIVES Most system designs require no signals other than those already provided by the BIU. However, heavily loaded bus conditions, slow memory or peripheral device performance and off-board de- vice interfaces may not be supported directly without modifying the BIU interface.
Page 115: Buffering The Data Bus
BUS INTERFACE UNIT 3.6.1 Buffering the Data Bus The BIU generates two control signals, DEN and DT/R, to control bidirectional buffers or trans- ceivers. The timing relationship of DEN and DT/R is shown in Figure 3-30. The following con- ditions require transceivers: •...
Page 116: Buffered Ad Bus System
BUS INTERFACE UNIT A19:16 Latch Address Bus Processor AD15:0 Address Memory Transceiver Data Data Bus Device DT/ R CPU Local Bus Buffered Bus A1095-0A Figure 3-31. Buffered AD Bus System In a fully buffered system, DEN directly drives the transceiver output enable. A partially buffered system requires that DEN be qualified with another signal to prevent the transceiver from going active for local bus accesses.
Page 117: Synchronizing Software And Hardware Events
BUS INTERFACE UNIT AD15:8 MCS0 AD7:0 DT/R Figure 3-32. Qualifying DEN with Chip-Selects 3.6.2 Synchronizing Software and Hardware Events The execution sequence of a program and hardware events occurring within a system are often asynchronous to each other. In some systems there may be a requirement to suspend program ex- ecution until an event (or events) occurs, then continue program execution.
Page 118: Using A Locked Bus
BUS INTERFACE UNIT The WAIT instruction suspends program execution until one of two events occurs: an interrupt is generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does not require that program execution be transferred to a new location (i.e., an interrupt routine is not executed).
Page 119: Using The Queue Status Signals
BUS INTERFACE UNIT In general, prefix bytes (such as LOCK) are considered extensions of the instructions they pre- cede. Interrupts, DMA requests and refresh requests that occur during execution of the prefix are not acknowledged until the instruction following the prefix completes (except for instructions that are servicing interrupts during their execution, such as HALT, WAIT and repeated string primitives).Note that multiple prefix bytes can precede an instruction.
Page 120: Multi-Master Bus System Designs
BUS INTERFACE UNIT CLKOUT QS0, QS1 A1059-0A Figure 3-33. Queue Status Timing MULTI-MASTER BUS SYSTEM DESIGNS The BIU supports protocols for transferring control of the local bus between itself and other de- vices capable of acting as bus masters. To support such a protocol, the BIU uses a hold request input (HOLD) and a hold acknowledge output (HLDA) as bus transfer handshake signals.
Page 121: Hold Bus Latency
BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 A19:16 RD, WR, DT/R, BHE, S2:0 LOCK NOTES: 1. T HVCL : HOLD input to clock low 2. T CHCZ : Clock high to output float 3. T CLAZ : Clock low to output float 4.
Page 122: Refresh Operation During A Bus Hold
The major factors that influence bus latency are listed below (in order from longest delay to short- est delay). Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be serviced. Locked Bus Cycle — As long as LOCK remains asserted, a bus hold request cannot be serviced.
Page 123: Refresh Request During Hold
BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 A19:16 RD, WR, BHE, S2:0 DT/R, LOCK NOTES: 1. HLDA is deasserted, signaling need to run refresh bus cycle. 2. External bus master terminates use of the bus. 3. HOLD deasserted. 4. Hold may be reasserted after one clock. 5.
Page 124: Exiting Hold
HLDA RESET HOLD The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is complete, the BIU will release the bus and generate HLDA.
Page 125: Bus Cycle Priorities
BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, DT/R, S2:0, A19:16, LOCK NOTES: 1. T HVCL : HOLD recognition setup to clock low : HOLD internally synchronized 3. T CLHAV : Clock low to HLDA low 4. T CHCV : Clock high to signal active (high or low) 5.
Page 126 Internal error (e.g., divide error, overflow) interrupt vectoring sequence. Hardware (e.g., INT0, DMA) interrupt vectoring sequence. 80C187 Math Coprocessor error interrupt vectoring sequence. DMA bus cycles. 10. General instruction execution. This category includes read/write operations following a pipelined effective address calculation, vectoring sequences for software interrupts and numerics code execution.
Page 128 Peripheral Control Block...
Page 130: Peripheral Control Registers
All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers within an integrated Peripheral Control Block (PCB). The peripheral control registers are physi- cally located in the peripheral devices they control, but they are addressed as a single block of registers.
Page 131: Pcb Relocation Register
PCB Base Address Upper Bits NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 4-1. PCB Relocation Register PCB Relocation Register RELREG Relocates the PCB within memory or I/O space.
Page 132: Peripheral Control Block
Table 4-1. Peripheral Control Block Function Offset Offset Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved POLL POLLSTS IMASK PRIMSK INSERV REQST INSTS TCUCON DMA0CON DMA1CON I0CON I1CON I2CON I3CON PERIPHERAL CONTROL BLOCK Function Function Offset...
Page 133: Reserved Locations
PERIPHERAL CONTROL BLOCK RESERVED LOCATIONS Many locations within the Peripheral Control Block are not assigned to any peripheral. Unused locations are reserved. Reading from these locations yields an undefined result. If reserved reg- isters are written (for example, during a block MOV instruction) they must be set to 0H. Failure to follow this guideline could result in incompatibilities with future 80C186 Modular Core family products.
Page 134: F-Bus Operation
4.4.3 F-Bus Operation The F-Bus functions differently than the external data bus for byte and word accesses. All write transfers on the F-Bus occur as words, regardless of how they are encoded. For example, the in- struction OUT DX, AL (DX is even) will write the entire AX register to the Peripheral Control Block register at location [DX].
Page 135: Writing The Pcb Relocation Register
PERIPHERAL CONTROL BLOCK 4.4.3.1 Writing the PCB Relocation Register Whenever mapping the Peripheral Control Block to another location, the user should program the Relocation Register with a byte write (i.e., OUT DX, AL). Internally, the Relocation Register is written with 16 bits of the AX register, while externally the Bus Interface Unit runs a single 8-bit bus cycle.
Page 136: Considerations For The 80C187 Math Coprocessor Interface
As an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, the user would program the PCB Relocation Register with the value 1100H. Since the Relocation Register is part of the Peripheral Control Block, it relocates to word 10000H plus its fixed offset. Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space.
Page 138 Clock Generation and Power Management...
Page 140: Clock Generation
CLOCK GENERATION AND POWER The clock generation and distribution circuits provide uniform clock signals for the Execution Unit, the Bus Interface Unit and all integrated peripherals. The 80C186 Modular Core Family processors have additional logic that controls the clock signals to provide power management functions.
Page 141: Oscillator Operation
CLOCK GENERATION AND POWER MANAGEMENT 5.1.1.1 Oscillator Operation A phase shift oscillator operates through positive feedback, where a non-inverted, amplified ver- sion of the input connects back to the input. A 360° phase shift around the loop will sustain the feedback in the oscillator.
Page 142: Crystal Connections To Microprocessor
Choose C and L component values in the third overtone crystal circuit to satisfy the following conditions: • The LC components form an equivalent series resonant circuit at a frequency below the fundamental frequency. This criterion makes the circuit inductive at the fundamental frequency.
Page 143: Equations For Crystal Calculations
CLOCK GENERATION AND POWER MANAGEMENT To examine the parallel resonant frequency, refer to Figure 5-3(c), an equivalent circuit to Figure 5-3(b). The capacitance connected to L tance is still about 200 pF (within 10%) and the equation in Figure 5-4(a) now yields the parallel resonant frequency.
Page 144: Selecting Crystals
5.1.1.2 Selecting Crystals When specifying crystals, consider these parameters: • Resonance and Load Capacitance — Crystals carry a parallel or series resonance specifi- cation. The two types do not differ in construction, just in test conditions and expected circuit application. Parallel resonant crystals carry a test load specification, with typical load capacitance values of 15, 18 or 22 pF.
Page 145: Using An External Oscillator
CLOCK GENERATION AND POWER MANAGEMENT An important consideration when using crystals is that the oscillator start correctly over the volt- age and temperature ranges expected in operation. Observe oscillator startup in the laboratory. Varying the load capacitors (within about ± 50%) can optimize startup characteristics versus sta- bility.
Page 146: Simple Rc Circuit For Powerup Reset
CLOCK GENERATION AND POWER MANAGEMENT Reset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RES input during power supply and oscillator startup. The processor’s pins assume their reset pin states a maximum of 28 X1 periods after X1 and V stabilize.
Page 147: Cold Reset Waveform
CLOCK GENERATION AND POWER MANAGEMENT V cc CLKOUT UCS, LCS MCS3:0, NCS TMR OUT0 TMR OUT1 PCS6:0 HLDA, ALE A19:16 AD15:0, S2:0 RD, WR, DEN DT/R, LOCK RESET NOTE: CLKOUT synchronization occurs 1 1/2 X1 periods after RES is sampled low. Figure 5-6.
Page 148: Warm Reset Waveform
CLKOUT UCS, LCS MCS3:0 PCS6:0,NCS TMR OUT0 TMR OUT1 HLDA, ALE A19/S6: AD15:0 S2:0, RD WR, DEN DT/R LOCK RESET Figure 5-7. Warm Reset Waveform At the second falling CLKOUT edge after sampling RES inactive, the processor deasserts RE- SET. Bus activity starts 6½ CLKOUT periods after recognition of RES in the logic high state. If an alternate bus master asserts HOLD during reset, the processor immediately asserts HLDA and will not prefetch instructions.
Page 149: Power Management
CLOCK GENERATION AND POWER MANAGEMENT RESYNC (Internal) CLKOUT RESET NOTES: 1. Setup of RES to falling X1. 2. RESYNC pulse generated. 3. RESYNC drives CLKOUT high, resynchronizing the clock generator. 4. RESET goes active. 5. RES allowed to go inactive after minimum 4 CLKOUT cycles. 6.
Page 150: Power-Save Mode
5.2.1 Power-Save Mode Power-Save mode is a means for reducing operating current. Power-Save mode enables a pro- grammable clock divider in the clock generation circuit. Power-Save mode can be used to stretch bus cycles as an alternative to wait states. Possible clock divisor settings are 1 (undivided), 4, 8 and 16.
Page 151: Power-Save Register
F1:0 Clock Division Factor NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 5-9. Power-Save Register 5-12 Power Save Register PWRSAV Enables and sets clock division factor.
Page 152: Leaving Power-Save Mode
CLKOUT NOTES: 1. : Write to Power-Save Register (as viewed on the bus). 2. : Low-going edge of T3 starts new clock rate. Figure 5-10. Power-Save Clock Transition 5.2.1.2 Leaving Power-Save Mode Power-Save mode continues until one of three events occurs: execution clears the PSEN bit in the Power-Save Register, an unmasked interrupt occurs or an NMI occurs.
Page 153: Initializing The Power Management Unit For Power-Save Mode
CLOCK GENERATION AND POWER MANAGEMENT $mod186 name example_PSU_code ;FUNCTION: This function reduces CPU power consumption by dividing the CPU operating frequency by a divisor. SYNTAX: extern void far power_save(int divisor); INPUTS: divisor - This variable represents F0, F1 and F2 of PWRSAV.
Page 154 Chip-Select Unit...
Page 156: Common Methods For Generating Chip-Selects
Every system requires some form of component-selection mechanism to enable the CPU to ac- cess a specific memory or peripheral device. The signal that selects the memory or peripheral de- vice is referred to as a chip-select. Besides selecting a specific device, each chip-select can be used to control the number of wait states inserted into the bus cycle.
Page 157: Chip-Select Unit Functional Overview
CHIP-SELECT UNIT 27C256 A0:12 A1:13 Chip-Selects Using Addresses Directly Figure 6-1. Common Chip-Select Generation Methods CHIP-SELECT UNIT FUNCTIONAL OVERVIEW The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the appropriate chip-select. Figure 6-3 illustrates the timing of a chip-select during a bus cycle. Note that the chip-select goes active in the same bus state as address goes active, eliminating any delay through address latches and decoder circuits.
Page 158: Chip-Select Block Diagram
Internal Address Bus = Block Size = Block Size = Block Size/4 = Block Size/4 = Base = Block Size/4 = Block Size/4 = Base Memory/ I/O Selector Internal Address Bit Figure 6-2. Chip-Select Block Diagram MCS3 MCS2 MCS1 MCS0 Base + 0 PCS0 Base + 128...
Page 159: Chip-Select Relative Timings
CHIP-SELECT UNIT Mapped only to the upper memory address space; selects the BOOT memory device (EPROM or Flash memory types). Mapped only to the lower memory address space; selects a static memory (SRAM) device that stores the interrupt vector table, local stack, local data, and scratch pad data.
Page 160: Ucs Reset Configuration
By combining LCS, UCS and MCS3:0, you can cover up to 786 Kbytes of memory address space. Methods such as those shown in Figure 6-1 on page 6-2 can be used to decode the remaining 256 Kbytes. The PCS6:0 chip-selects access a contiguous, 896-byte block of memory or I/O address space. Each chip-select goes active for one-seventh of the block (128 bytes).
Page 161: Programming
CHIP-SELECT UNIT PROGRAMMING Four registers determine the operating characteristics of the chip-selects. The Peripheral Control Block defines the location of the Chip-Select Unit registers. Table 6-1 lists the registers and their associated programming names. Table 6-1. Chip-Select Unit Registers Control Register Mnemonic UMCS LMCS...
Page 162: Umcs Register Definition
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Programming U17:10 with values other than those shown in Table 6-2 on page 6-12 results in unreliable chip-select operation.
Page 163: Lmcs Register Definition
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Programming U17:10 with values other than those shown in Table 6.3 on page 6-13 results in unreliable chip-select operation.
Page 164: Mmcs Register Definition
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A starting address other than an integer multiple of the block size defined in the MPCS register causes unreliable chip-select operation.
Page 165: Pacs Register Definition
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. U19:16 must be programmed to zero for proper I/O bus cycle operation. Reading this register and the MPCS register (before writing them) enables the PCS chip-selects;...
Page 166: Mpcs Register Definition
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A starting address other than an integer multiple of the block size defined in this register causes unreliable chip-select operation.
Page 167: Programming The Active Ranges
CHIP-SELECT UNIT The UMCS and LMCS registers can be programmed in any sequence. To program the MCS and PCS chip-selects, follow this sequence: Program the MPCS register Program the MMCS register to enable the MCS chip-selects. Program the PACS register to enable the PCS chip-selects. 6.4.2 Programming the Active Ranges The active ranges of the chip-selects are determined by a combination of their starting or ending...
Page 168: Lcs Active Range
6.4.2.2 LCS Active Range The LCS starting address is fixed at zero in memory address space; its ending address is the pro- grammed block size minus one. Table 6.3 defines the acceptable values for the field (U17:10) in the LMCS register that determines the LCS block size and ending address. Table 6.3 LCS Active Range LMCS Field U17:10...
Page 169: Mcs3:0 Active Ranges
CHIP-SELECT UNIT Table 6-5. MCS Block Size and Start Address Restrictions MPCS Block Size Bits X= don’t care, but should be 0 for future compatibility. Starting Address Block Size is defined by M6:0 Base + 3/4 Block Size Base + 1/2 Block Size Base + 1/4 Block Size MCS Base (Defined by U19:13)
Page 170: Pcs Active Range
6.4.2.4 PCS Active Range Each PCS chip-select starts at an offset above the base address programmed in the PACS register and is active for 128 bytes. The base address can start on any 1 Kbyte memory or I/O address location. Table 6-6 lists the active range for each PCS chip-select. Chip- Select PCS0...
Page 171: Overlapping Chip-Selects
CHIP-SELECT UNIT BUS READY R2 Control Bit Wait State Value (R1:0) Figure 6-11. Wait State and Ready Control Functions The R2 control bit determines whether the bus cycle completes normally (requires bus ready) or unconditionally (ignores bus ready). The R1:0 bits define the number of wait states to insert into the bus cycle.
Page 172: Memory Or I/O Bus Cycle Decoding
When programming the PCS chip-selects active for I/O bus cycles, remember that eight bytes of I/O are reserved by Intel. These eight bytes (locations 00F8H through 00FFH) control the inter- face to an 80C187 math coprocessor. A chip-select can overlap this reserved space provided there is no intention of using the 80C187.
Page 173: Chip-Selects And Bus Hold
CHIP-SELECT UNIT CHIP-SELECTS AND BUS HOLD The Chip-Select Unit decodes only internally generated address and bus state information. An ex- ternal bus master cannot make use of the Chip-Select Unit. During HLDA, all chip-selects remain inactive. The circuit shown in Figure 6-12 allows an external bus master to access a device during bus HOLD.
Page 174: Typical System
Processor ARDY SRDY A19:16 Addr AD Bus AD15:0 PCS1 MCS3:0 PCS0 Figure 6-13. Typical System EPROM 128K 256K CHIP-SELECT UNIT SRAM Floppy Disk Control DACK A1138-0A 6-19...
Page 175: Initializing The Chip-Select Unit
CHIP-SELECT UNIT TITLE MOD186XREF NAME ; External reference from this module include(PCBMAP.INC ; Module equates ; Configuration equates INTRDY EQU EXTRDY EQU ALLPCS EQU ;Below is a list of the default system memory and I/O environment. These ;defaults configure the Chip-Select Unit for proper system operation. ;EPROM memory is located from 0E0000 to 0FFFFF (128 Kbytes).
Page 176 DRAM_BASE DRAM_SIZE DRAM_WAIT DRAM_RDY INTRDY ;The MPCS register is used to program both the MCS and PCS chip-selects. ;Below are the equates for the I/O peripherals (also used to program the PACS ;register. IO_WAIT IO_RDY INTRDY PCS_SPACE PCS_FUNC ALLPCS ;The MMCS and MPCS register values are calculated using the above system ;constraints and the equations below: MMCS_VAL (DRAM_BASE SHL 6) OR (001F8H) OR (DRAM_RDY) OR (DRAM_WAIT)
Page 177 CHIP-SELECT UNIT dx, MPCS_REG ax, MPCS_VAL dx, al dx, MMCS_REG ax, MMCS_VAL dx, al dx, PACS_REG ax, PACS_VAL dx, al CODE ENDS ;Power-on reset code to get started ASSUME CS:POWER_ON POWER_ON SEGMENT AT 0FFFFH dx, UMCS_REG ax, UMCS_VAL dx, al FW_START POWER_ON ENDS...
Page 178 Refresh Control Unit...
Page 180: Refresh Control Unit Block Diagram
The Refre h Control Unit (RCU) simplifies dynamic memory controller design with its integrat- ed address and clock counters. Figure 7-1 shows the relationship between the Bus Interface Unit and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an external DRAM controller to use chip-selects, wait state logic and status lines.
Page 181: The Role Of The Refresh Control Unit
REFRESH CONTROL UNIT THE ROLE OF THE REFRESH CONTROL UNIT Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution. Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor does it transfer data.
Page 182: Refresh Control Unit Operation Flow Chart
Refresh Control Unit Operation Set "E" Bit Load Counter From Refresh Clock Interval Register Counter = ? Decrement Counter Generated BIU Request Figure 7-2. Refresh Control Unit Operation Flow Chart The nine-bit refresh clock counter does not wait until the BIU services the refresh request to con- tinue counting.
Page 183: Refresh Addresses
REFRESH CONTROL UNIT The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another request before the BIU handles the present request, the BIU loses the present request. However, the address associated with the request is not lost. The refresh address changes only after the BIU runs a refresh bus cycle.
Page 184: Guidelines For Designing Dram Controllers
REFRESH BUS CYCLES Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control sig- nals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh bus cycle. The 16-bit bus processor drives both the BHE and A0 pins high during refresh cycles. The 8-bit bus version replaces the BHE pin with RFSH, which has the same timings.
Page 185: Suggested Dram Control Signal Timing Relationships
REFRESH CONTROL UNIT CLKOUT Muxed Address S2:0 NOTES: 1. CAS is unnecessary for refresh cycles only. 2. WE is necessary for write cycles only. Figure 7-4. Suggested DRAM Control Signal Timing Relationships The cycle begins with presentation of the row address. RAS should go active on the falling edge of T2.
Page 186: Programming The Refresh Control Unit
PROGRAMMING THE REFRESH CONTROL UNIT Given a specific processor operating frequency and information about the DRAMs in the system, the user can program the Refresh Control Unit registers. 7.7.1 Calculating the Refresh Interval DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles.
Page 187: Refresh Base Address Register
RA19:13 Refresh Base NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-6. Refresh Base Address Register 7.7.2.2 Refresh Clock Interval Register The Refresh Clock Interval Register (Figure 7-7) defines the time between refresh requests. The higher the value, the longer the time between requests.
Page 188: Refresh Control Register
RC8:0 Refresh Counter Reload Value NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-7. Refresh Clock Interval Register 7.7.2.3 Refresh Control Register Figure 7-8 shows the Refresh Control Register.
Page 189: Programming Example
RC8:0 Refresh Counter NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-8. Refresh Control Register 7.7.3 Programming Example Example 7-1 contains sample code to initialize the Refresh Control Unit. Example 5-2 on page 5-14 shows the additional code to reprogram the Refresh Control Unit upon entering Power-Save mode.
Page 190: Initializing The Refresh Control Unit
$mod186 name example_80C186_RCU_code ; FUNCTION: This function initializes the DRAM Refresh ; Control Unit to refresh the DRAM starting at dram_addr ; at clock_time intervals. ; SYNTAX: ; extern void far config_rcu(int dram_addr, int clock_time); ; INPUTS: dram_addr clock_time - DRAM refresh rate ;...
Page 191: Refresh Operation And Bus Hold
REFRESH CONTROL UNIT dx, RFBASE ax, _dram_addr dx, al dx, RFTIME ax, _clock_time dx, al dx, RFCON ax, Enable dx, al cx, 8 di, di _exercise_ram: word ptr [di], 0 loop _exercise_ram _config_rcu endp lib_80186 ends Example 7-1. Initializing the Refresh Control Unit (Continued) REFRESH OPERATION AND BUS HOLD When another bus master controls the bus, the processor keeps HLDA active as long as the HOLD input remains active.
Page 192: Regaining Bus Control To Run A Dram Refresh Bus Cycle
CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, S2:0 DT / R, A19:16 NOTES: 1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T CLHAV . 2. External bus master terminates use of the bus. 3. HOLD deasserted; greater than T HVCL . 4.
Page 194 Interrupt Control Unit...
Page 196: Functional Overview
The 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and Exception Handling” on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities be- yond a single input. To fulfill this function, the Interrupt Control Unit operates in either of two modes: Master or Slave.
Page 197: Master Mode
INTERRUPT CONTROL UNIT Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires servicing. The CPU then stops executing the main task, saves its state and transfers execution to the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the CPU’s original state is restored and execution continues at the point of interruption in the main task.
Page 198: Interrupt Masking
8.2.1.1 Interrupt Masking There are circumstances in which a programmer may need to disable an interrupt source tempo- rarily (for example, while executing a time-critical section of code or servicing a high-priority task). This temporary disabling is called interrupt masking. All interrupts from the Interrupt Con- trol Unit can be masked either globally or individually.
Page 199: Interrupt Nesting
INTERRUPT CONTROL UNIT The priority of each source is programmable. The Interrupt Control register enables the programmer to assign each source a priority that differs from the default. The priority must still be between zero (highest) and seven (lowest). Interrupt sources can be programmed to share a priority.
Page 200: Functional Operation In Master Mode
FUNCTIONAL OPERATION IN MASTER MODE This section covers the process in which the Interrupt Control Unit receives interrupts and asserts the maskable interrupt request to the CPU. 8.3.1 Typical Interrupt Sequence When the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the In- terrupt Request register to indicate that the interrupt is pending.
Page 201: Priority Resolution Example
INTERRUPT CONTROL UNIT 8.3.2.1 Priority Resolution Example This example illustrates priority resolution. Assume these initial conditions: • the Interrupt Control Unit has been initialized • no interrupts are pending • no In-Service bits are set • the Interrupt Enable bit is set •...
Page 202: Interrupts That Share A Single Source
INTERRUPT CONTROL UNIT 8.3.2.2 Interrupts That Share a Single Source Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit. (For example, the three timers share a single input.) Although these interrupts share an input, each has its own interrupt vector.
Page 203: Special Fully Nested Mode
INTERRUPT CONTROL UNIT 8259A 82C59A INTA 8259A 82C59A INTA Figure 8-2. Using External 8259A Modules in Cascade Mode 8.3.3.1 Special Fully Nested Mode Special fully nested mode is an optional feature normally used with cascade mode. It is applicable only to INT0 and INT1. In special fully nested mode, an interrupt request is serviced even if its In-Service bit is set.
Page 204: Interrupt Acknowledge Sequence
8.3.4 Interrupt Acknowledge Sequence During the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrupt type to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector ad- dress in the interrupt vector table. (“Interrupt/Exception Processing” on page 2-39 describes the interrupt acknowledge sequence and Figure 2-25 on page 2-40 illustrates the interrupt vector ta- ble.) The interrupt types for all sources are fixed and unalterable (see Table 8-2).
Page 205: Edge And Level Triggering
INTERRUPT CONTROL UNIT 8.3.6 Edge and Level Triggering The external interrupts (INT3:0) can be programmed for either edge or level triggering (see “In- terrupt Control Registers” on page 8-12). Both types of triggering are active high. An edge-trig- gered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must remain high until after the CPU acknowledges the interrupt, then must go low to reset the edge- detection circuitry.
Page 206: Programming The Interrupt Control Unit
Interrupt presented to control unit Interrupt presented to CPU First instruction fetch from interrupt routine Figure 8-3. Interrupt Control Unit Latency and Response Time PROGRAMMING THE INTERRUPT CONTROL UNIT Table 8-3 lists the Interrupt Control Unit registers in master mode with their Peripheral Control Block offset addresses.
Page 207: Interrupt Control Registers
INTERRUPT CONTROL UNIT Table 8-3. Interrupt Control Unit Registers in Master Mode (Continued) In-Service Priority Mask Interrupt Mask Poll Status Poll 8.4.1 Interrupt Control Registers Each interrupt source has its own Interrupt Control register. The Interrupt Control register allows you to define the behavior of each interrupt source. Figure 8-4 shows the registers for the timers and DMA channels, Figure 8-5 shows the registers for INT3:2, and Figure 8-6 shows the registers for INT0 and INT1.
Page 208: Interrupt Control Register For Internal Sources
Priority Level NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-4. Interrupt Control Register for Internal Sources INTERRUPT CONTROL UNIT Interrupt Control Register (internal sources)
Page 209: Interrupt Control Register For Noncascadable External Pins
Priority Level NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-5. Interrupt Control Register for Noncascadable External Pins 8-14 Interrupt Control Register (non-cascadable pins)
Page 210: Interrupt Control Register For Cascadable Interrupt Pins
Priority Level NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins INTERRUPT CONTROL UNIT Interrupt Control Register (cascadable pins)
Page 211: Interrupt Request Register
Interrupt Timer Interrupt NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-7. Interrupt Request Register 8.4.3 Interrupt Mask Register The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source. This reg- ister allows you to mask (disable) individual interrupts.
Page 212: Priority Mask Register
Timer Interrupt Mask NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-8. Interrupt Mask Register 8.4.4 Priority Mask Register The Priority Mask register (Figure 8-9) contains a three-level field that holds a priority value.
Page 213: In-Service Register
PM2:0 Priority Mask NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-9. Priority Mask Register 8.4.5 In-Service Register The In-Service register has a bit for each interrupt source. The bits indicate which source’s inter- rupt handlers are currently executing.
Page 214: Poll And Poll Status Registers
Timer Interrupt In- Service NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-10. In-Service Register 8.4.6 Poll and Poll Status Registers The Poll and Poll Status registers allow you to poll the Interrupt Control Unit and service inter- rupts through software.
Page 215: Poll Register
Request VT4:0 Vector Type NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. 8-20 Poll Register POLL Read to check for and acknowledge pending...
Page 216: End-Of-Interrupt (Eoi) Register
Request VT4:0 Vector Type NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-12. Poll Status Register 8.4.7 End-of-Interrupt (EOI) Register The End-of-Interrupt register (Figure 8-13) issues an End-of-Interrupt (EOI) command to the In- terrupt Control Unit, which clears the In-Service bit for the associated interrupt.
Page 217: Interrupt Status Register
VT4:0 Interrupt Type NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-13. End-of-Interrupt Register 8.4.8 Interrupt Status Register The Interrupt Status register (Figure 8-14) contains the DMA Halt bit and one bit for each timer interrupt.
Page 218: Slave Mode
Pending NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-14. Interrupt Status Register Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled.
Page 219: Interrupt Control Unit In Slave Mode
INTERRUPT CONTROL UNIT INT0 INTA 80186 Modular Core Select Figure 8-15. Interrupt Control Unit in Slave Mode 8-24 V CC 8259A/ 82C59A INTA Cascade Address Decode A1194-A0...
Page 220: Slave Mode Programming
INTERRUPT CONTROL UNIT Timer 0 Timer 1 Timer 2 Interrupt Priority Resolver Vector To External 8259A Generation Interrupt Request Logic F - Bus A1195-A0 Figure 8-16. Interrupt Sources in Slave Mode 8.5.1 Slave Mode Programming Some registers differ between Slave mode and Master mode. Slave mode adds the Interrupt Vec- tor Register;...
Page 221: Interrupt Vector Register
INTERRUPT CONTROL UNIT 8.5.1.1 Interrupt Vector Register The Interrupt Vector Register is used only in Slave mode. In Master mode, the interrupt vector types are fixed; in Slave mode they are programmable. The Interrupt Vector Register is used to specify the five most-significant bits of the interrupt vector type. The three least-significant bits are fixed (Table 8-5).
Page 222: End-Of-Interrupt Register
Interrupt Vector Type Field NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-17. Interrupt Vector Register (Slave Mode Only) 8.5.1.2 End-Of-Interrupt Register The End-of-Interrupt (EOI) register has the same function in Slave mode as in Master mode.
Page 223: Other Registers
VT2:0 Interrupt Type NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-18. End-of-Interrupt Register in Slave Mode 8.5.1.3 Other Registers The Priority Mask register is identical in Slave mode and Master mode. The Interrupt Request,...
Page 224: Interrupt Vectoring In Slave Mode
8.5.2 Interrupt Vectoring in Slave Mode In Slave mode, the external 8259A module acts as the master interrupt controller. Therefore, in- terrupt acknowledge cycles are required for every interrupt, including those from integrated pe- ripherals. During the first interrupt acknowledge cycle, the external 8259A determines which slave interrupt controller has the highest priority interrupt request.
Page 225: Initializing The Interrupt Control Unit For Master Mode
INTERRUPT CONTROL UNIT External interrupt acknowledge cycles must be run for every maskable interrupt. Therefore, the interrupt response time for every interrupt will be 55 clocks, as shown in Figure 8-21. Interrupt presented to Interrupt Control Unit Interrupt presented to external 82C59A First instruction fetch from interrupt routine Figure 8-21.
Page 226: Initializing The Interrupt Control Unit For Master Mode
Set the mask bit in the Interrupt Mask register for any interrupts that you wish to disable. Example 8-1 shows sample code to initialize the Interrupt Control Unit. $mod186 name example_80C186_ICU_initialization ;This routine configures the interrupt controller to provide two cascaded ;interrupt inputs (through an external 8259A connected to INT0 and INTA0#) ;and two direct interrupt inputs connected to INT1 and INT3.
Page 228 Timer/Counter Unit...
Page 230: Functional Overview
CHAPTER 9 TIMER/COUNTER UNIT The Timer/Counter Unit can be used in many applications. Some of these applications include a real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented in a system design. A real-time clock can be used to update time-dependent memory variables. A square-wave generator can be used to provide a system clock tick for peripheral devices.
Page 231: Timer/Counter Unit Block Diagram
TIMER/COUNTER UNIT Transition Latch/ Synchronizer Timer 0 Registers Timer 1 Registers Timer 2 Registers Clock Figure 9-1. Timer/Counter Unit Block Diagram T0 In T1 In Transition Latch/ Synchronizer Output Latch Counter Element Output Latch Interrupt Latch A1292-0A...
Page 232: Counter Element Multiplexing And Timer Input Synchronization
Timer 0 Timer 1 Serviced Serviced T0IN T1IN T0OUT T1OUT NOTES: 1. T0IN resolution time (setup time met). 2. T1IN resolution time (setup time not met). 3. Modified count value written into Timer 0 count register. 4. T1IN resolution time, count value written into Timer 1 count register. 5.
Page 233: Timers 0 And 1 Flow Chart
TIMER/COUNTER UNIT Start Retrigger (RTG = 1) Timer Input at High Level Prescaler On (P = 1) Did Timer 2 Reach Maxcount Last Service State Done Figure 9-3. Timers 0 and 1 Flow Chart Timer Enabled (EN = 1) External Clocking (EXT = 1) Lo to Hi...
Page 234 Counter = Compare "A" Done Pulse TOUT Pin Low For 1 Clock Continuous Mode (CONT=1) Clear Enable Bit (Stop Counting) Figure 9-3. Timers 0 and 1 Flow Chart (Continued) Continued From "A" Alternating Maxcount Regs (ALT = 1) Using (Use"A") Maxcount A (RIU = 0) Counter =...
Page 235: Programming The Timer/Counter Unit
TIMER/COUNTER UNIT When configured for internal clocking, the Timer/Counter Unit uses the input pins either to en- able timer counting or to retrigger the associated timer. Externally, a timer increments on low-to- high transitions on its input pin (up to ¼ CLKOUT frequency). Timers 0 and 1 each have a single output pin.
Page 236: Timer 0 And Timer 1 Control Registers
Count NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-5. Timer 0 and Timer 1 Control Registers Timer 0 and 1 Control Registers T0CON, T1CON Defines Timer 0 and 1 operation.
Page 237 Mode NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued) Timer 0 and 1 Control Registers T0CON, T1CON Defines Timer 0 and 1 operation.
Page 238: Timer 2 Control Register
CONT Continuous Mode NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-6. Timer 2 Control Register Timer 2 Control Register T2CON Defines Timer 2 operation.
Page 239: Timer Count Registers
TIMER/COUNTER UNIT Register Name: Register Mnemonic: Register Function: Bit Name Mnemonic TC15:0 Timer Count Value Figure 9-7. Timer Count Registers 9-10 Timer Count Register T0CNT, T1CNT, T2CNT Contains the current timer count. Reset Function State XXXXH Contains the current count of the associated timer.
Page 240: Initialization Sequence
Register Name: Register Mnemonic: Register Function: Bit Name Mnemonic TC15:0 Timer Compare Value Figure 9-8. Timer Maxcount Compare Registers 9.2.1 Initialization Sequence When initializing the Timer/Counter Unit, the following sequence is suggested: If timer interrupts will be used, program interrupt vectors into the Interrupt Vector Table. Clear the Timer Count register.
Page 241: Clock Sources
TIMER/COUNTER UNIT 9.2.2 Clock Sources The 16-bit Timer Count register increments once for each timer event. A timer event can be a low-to-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU clock (all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (2 Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer events by setting the External (EXT) bit in their control registers.
Page 242: Retriggering
TIMER/COUNTER UNIT The timer counting from its initial count (usually zero) to its maximum count (either Maxcount Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of 0 implies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count of 1, etc.
Page 243: Pulsed And Variable Duty Cycle Output
TIMER/COUNTER UNIT Timer counts internal events, if input pin remains high. Timer counts internal events; count resets to zero on every low-to-high transition on the input pin. Timer input acts as clock source. When the EXT bit is clear and the RTG bit is set, every low-to-high transition on the timer input pin causes the Count register to reset to zero.
Page 244: Enabling/Disabling Counters
TIMER/COUNTER UNIT Timer 0 Serviced Internal Count Value Maxcount - 1 TxOUT Pin NOTE: 1. T CLOV1 A1301-0A Figure 9-9. TxOUT Signal Timing In dual maximum count mode, the timer output pin indicates which Maxcount Compare register is currently in use. A low output indicates Maxcount Compare B, and a high output indicates Maxcount Compare A (see Figure 9-4 on page 9-6).
Page 245: Timer Interrupts
TIMER/COUNTER UNIT The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer counting. When using internal clocking, the input pin can be programmed either to enable the tim- er or to reset the timer count, depending on the state of the Retrigger (RTG) bit in the control reg- ister.
Page 246: Synchronization And Maximum Frequency
9.3.2 Synchronization and Maximum Frequency All timer inputs are latched and synchronized with the CPU clock. Because of the internal logic required to synchronize the external signals, and the multiplexing of the counter element, the Timer/Counter Unit can operate only up to ¼ of the CLKOUT frequency. Clocking at greater fre- quencies will result in missed clocks.
Page 247: Configuring A Real-Time Clock
TIMER/COUNTER UNIT $mod186 name example_80186_family_timer_code ;FUNCTION: This function sets up the timer and interrupt controller to cause the timer to generate an interrupt every 10 milliseconds and to service interrupts to implement a real time clock. Timer 2 is used in this example because no input or output signals are required.
Page 248 lib_80186 segment public ’code’ assume cs:lib_80186, ds:data public _set_time _set_time proc far push bp, sp hour equ word ptr[bp+6] minute equ word ptr[bp+8] second equ word ptr[bp+10] T2Compare equ word ptr[bp+12] push push push push ax, ax ds, ax si, 4*timer_2_int word ptr ds:[si], offset timer_2_interrupt_routine ds:[si], cs...
Page 249 TIMER/COUNTER UNIT _set_time endp timer_2_interrupt_routine proc far push push _msec, 99 bump_second _msec short reset_int_ctl bump_second: _msec, 0 _minute, 59 bump_minute _second short reset_int_ctl bump_minute: _second, 0 _minute, 59 bump_hour _minute short reset_int_ctl bump_hour: _minute, 0 _hour, 12 reset_hour _hour reset_int_ctl reset_hour: _hour, 1...
Page 250: Configuring A Square-Wave Generator
$mod186 name example_timer1_square_wave_code ;FUNCTION: This function generates a square wave of given frequency and duty cycle on Timer 1 output pin. SYNTAX: extern void far clock(int mark, int space) INPUTS: mark - This is the mark (1) time. space - This is the space (0) time. The register compare value for a given time can be easily calculated from the formula below.
Page 251: Configuring A Digital One-Shot
TIMER/COUNTER UNIT _clock endp lib_80186 ends Example 9-2. Configuring a Square-Wave Generator (Continued) $mod186 name example_timer1_1_shot_code ; FUNCTION: This function generates an active-low one-shot pulse on Timer 1 output pin. ; SYNTAX: extern void far one_shot(int CMPB); ; INPUTS: CMPB - This is the T1CMPB value required to generate a pulse of a given pulse width.
Page 252 _CMPB equ word ptr[bp+6] push push dx, T1CNT ax, ax dx, al dx, T1CMPA ax, 1 dx, al dx, T1CMPB ax, _CMPB dx, al dx, T1CON ax, C002H dx, al CountDown: in ax, dx test ax, MaxCount CountDown ax, not MaxCount dx, al _one_shot endp...
Page 254 Direct Memory Access Unit...
Page 256: The Dma Transfer
CHAPTER 10 DIRECT MEMORY ACCESS UNIT In many applications, large blocks of data must be transferred between memory and I/O space. A disk drive, for example, usually reads and writes data in blocks that may be thousands of bytes long. If the CPU were required to handle each byte of the transfer, the main tasks would suffer a severe performance penalty.
Page 257: Typical Dma Transfer
DIRECT MEMORY ACCESS UNIT When the DMA request is granted, the Bus Interface Unit provides the bus signals for the DMA transfer, while the DMA channel provides the address information for the source and destination devices. The DMA Unit does not provide a discrete DMA acknowledge signal, unlike other DMA controller chips (an acknowledge can be synthesized, however).
Page 258: Dma Transfer Directions
10.1.1.1 DMA Transfer Directions The source and destination addresses for a DMA transfer are programmable and can be in either memory or I/O space. DMA transfers can be programmed for any of the following four direc- tions: • from memory space to I/O space •...
Page 259: Dma Request Minimum Response Time
DIRECT MEMORY ACCESS UNIT 10.1.4 External Requests External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUT. It takes a minimum of four clocks before the DMA cycle is initiated by the BIU (see Figure 10-2).
Page 260: Source-Synchronized Transfers
10.1.4.1 Source Synchronization A typical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripherals deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deas- serted at least four clocks before the end of the DMA transfer (at the T1 state of the deposit phase) to prevent another DMA cycle from occurring.
Page 261: Destination-Synchronized Transfers
DIRECT MEMORY ACCESS UNIT Fetch Cycle CLKOUT (Case 1) (Case 2) NOTES: 1. Current destination synchronized transfer will not be immediately followed by another DMA transfer. 2. Current destination synchronized transfer will be immediately followed by another DMA transfer. Figure 10-4. Destination-Synchronized Transfers 10.1.5 Internal Requests Internal DMA requests can come from either Timer 2 or the system software.
Page 262 10.1.6 DMA Transfer Counts Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total number of transfers the channel runs. The transfer count is decremented by one after each transfer (regardless of data size). The DMA channel can be programmed to terminate transfers when the transfer count reaches zero (also referred to as terminal count).
Page 263 DIRECT MEMORY ACCESS UNIT 10.1.8 DMA Unit Interrupts Each DMA channel can be programmed to generate an interrupt request when its transfer count reaches zero. 10.1.9 DMA Cycles and the BIU The DMA Unit uses the Bus Interface Unit to perform its transfers. When the DMA Unit has a pending request, it signals the BIU.
Page 264: Two-Channel Dma Module
DIRECT MEMORY ACCESS UNIT The last point is extremely important when the two channels use different synchronization. For example, consider the case in which channel 1 is programmed for high priority and destination synchronization and channel 0 is programmed for low priority and source synchronization. If a DMA request occurs for both channels simultaneously, channel 1 performs the first transfer.
Page 265: Examples Of Dma Priority
DIRECT MEMORY ACCESS UNIT Both Requests Asserted Channel Priority Channel 1 Channel 0 Channel 1 Channel 0 Synch Channel Priority High Channel 0 Synch Channel Priority High Channel 0 Synch Dest Figure 10-6. Examples of DMA Priority 10.1.10.1.2 Rotating Priority Channel priority rotates when the channels are programmed as both high or both low priority.
Page 266: Dma Source Pointer (High-Order Bits)
Source Address NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-7. DMA Source Pointer (High-Order Bits) DIRECT MEMORY ACCESS UNIT DMA Source Address Pointer (High) DxSRCH Contains the upper 4 bits of the DMA Source pointer.
Page 267: Dma Source Pointer (Low-Order Bits)
DIRECT MEMORY ACCESS UNIT Register Name: Register Mnemonic: Register Function: Bit Name Mnemonic DSA15:0 Source Address Figure 10-8. DMA Source Pointer (Low-Order Bits) The address space referenced by the source and destination pointers is programmed in the DMA Control Register for the channel (see Figure 10-11 on page 10-15). The SMEM and DMEM bits control the address space (memory or I/O) for source pointer and destination pointer, respective- Automatic pointer indexing is also controlled by the DMA Control Register.
Page 268: Dma Destination Pointer (High-Order Bits)
Destination Address NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-9. DMA Destination Pointer (High-Order Bits) DIRECT MEMORY ACCESS UNIT DMA Destination Address Pointer (High)
Page 269: Dma Destination Pointer (Low-Order Bits)
DIRECT MEMORY ACCESS UNIT Register Name: Register Mnemonic: Register Function: Bit Name Mnemonic DDA15:0 Destination Address Figure 10-10. DMA Destination Pointer (Low-Order Bits) 10.2.1.2 Selecting Byte or Word Size Transfers The WORD bit in the DMA Control Register (Figure 10-11) controls the data size for a channel. When WORD is set, the channel transfers data in 16-bit words.
Page 270: Dma Control Register
Increment NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A pointer remains constant if its increment and decrement bits are equal. Figure 10-11. DMA Control Register...
Page 271 IDRQ Internal Request Select NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-11. DMA Control Register (Continued) 10-16 DMA Control Register DxCON Controls DMA channel parameters.
Page 272 Transfer Select NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-11. DMA Control Register (Continued) 10.2.1.3 Selecting the Source of DMA Requests DMA requests can come from either an internal source (Timer 2) or an external source.
Page 273 DIRECT MEMORY ACCESS UNIT 10.2.1.4 Arming the DMA Channel Each DMA channel must be armed before it can recognize DMA requests. A channel is armed by setting its STRT (Start) bit in the DMA Control Register (Figure 10-11 on page 10-15). The STRT bit can be modified only if the CHG (Change Start) bit is set at the same time.
Page 274: Transfer Count Register
Register Name: Register Mnemonic: Register Function: Bit Name Mnemonic TC15:0 Transfer Count Figure 10-12. Transfer Count Register The TC bit, when set, instructs the DMA channel to disarm itself (by clearing the STRT bit) when the transfer count reaches zero. If the TC bit is cleared, the channel continues to perform transfers regardless of the state of the Transfer Count Register.
Page 275 DIRECT MEMORY ACCESS UNIT 10.2.2 Suspension of DMA Transfers Whenever the CPU receives an NMI, all DMA activity is suspended at the end of the current transfer. The CPU suspends DMA activity by setting the DHLT bit in the Interrupt Status Regis- ter (Figure 8-14 on page 8-23).
Page 276 10.3.2 DMA Latency DMA Latency is the delay between a DMA request being asserted and the DMA cycle being run. The DMA latency for a channel is controlled by many factors: • Bus HOLD — Bus HOLD takes precedence over internal DMA requests. Using bus HOLD will degrade DMA latency.
Page 277 DIRECT MEMORY ACCESS UNIT 10.3.4 Generating a DMA Acknowledge The DMA channels do not provide a distinct DMA acknowledge signal. A chip-select line can be programmed to activate for the memory or I/O range that requires the acknowledge. The chip- select must be programmed to activate only when a DMA is in progress.
Page 278: Initializing The Dma Unit
$MOD186 name DMA_EXAMPLE_1 ; This example shows code necessary to set up two DMA channels. ; One channel performs an unsynchronized transfer from memory to memory. ; The second channel is used by a hard disk controller located in ; I/O space. ;...
Page 279 DIRECT MEMORY ACCESS UNIT DX, D0DSTH AX, BX DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. AX, 29 DX, D0TC DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE -----------...
Page 280 AX, 512 SECTORS DX, D1TC DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE ----------- ------ MEMORY SPACE I/O SPACE INCREMENT PTR CONSTANT PTR ; TERMINATE ON TC, INTERRUPT, SOURCE SYNC, HIGH PRIORITY RELATIVE TO ;...
Page 281: Timed Dma Transfers
DIRECT MEMORY ACCESS UNIT $mod186 name DMA_EXAMPLE_1 ; This example sets up the DMA Unit to perform a transfer from memory to ; I/O space every 22 uS. The data is sent to an A/D converter. ; It is assumed that the constants for PCB register addresses are ;...
Page 282 ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE ----------- ------ I/O SPACE MEMORY SPACE CONSTANT PTR INCREMENT PTR ; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS, ; LOW PRIORITY RELATIVE TO CHANNEL 1, BYTE XFERS. AX, 0001011101010110B DX, D0CON DX, AX...
Page 284 Math Coprocessing...
Page 286 80C187 has only a 5-volt rating. Please refer to the current data sheets for details. To execute numerics instructions, the 80C186XL must exit reset in Enhanced Mode. The pro- cessor checks its TEST pin at reset and automatically enters Enhanced Mode if the math copro- cessor is present.
Page 287 MATH COPROCESSING The core has an Escape Trap (ET) bit in the PCB Relocation Register (Figure 4-1 on page 4-2) to control the availability of math coprocessing. If the ET bit is set, an attempted numerics execution results in a Type 7 interrupt. The 80C187 will not work with the 8-bit bus version of the processor because all 80C187 accesses must be 16-bit.
Page 288: C187 Data Transfer Instructions
11.3.1.1 Data Transfer Instructions Data transfer instructions move operands between elements of the 80C187 register stack or be- tween stack top and memory. Instructions can convert any data type to temporary real and load it onto the stack in a single operation. Conversely, instructions can convert a temporary real oper- and on the stack to any data type and store it to memory in a single operation.
Page 289: C187 Arithmetic Instructions
MATH COPROCESSING Available data types include temporary real, long real, short real, short integer and word integer. The 80C187 performs automatic type conversion to temporary real. Table 11-2. 80C187 Arithmetic Instructions Addition FADD Add real FADDP Add real and pop FIADD Integer add Subtraction...
Page 290: Transcendental Instructions
11.3.1.3 Comparison Instructions Each comparison instruction (see Table 11-3) analyzes the stack top element, often in relationship to another operand. Then it reports the result in the Status Word condition code. The basic oper- ations are compare, test (compare with zero) and examine (report tag, sign and normalization). Table 11-3.
Page 291: Constant Instructions
MATH COPROCESSING 11.3.1.5 Constant Instructions Each constant instruction (see Table 11-5) loads a commonly used constant onto the stack. The values have full 80-bit precision and are accurate to about 19 decimal digits. Since a temporary real constant occupies 10 memory bytes, the constant instructions, only 2 bytes long, save mem- ory space.
Page 292: C187 Data Types
11.3.2 80C187 Data Types The microprocessor/math coprocessor combination supports seven data types: • Word Integer — A signed 16-bit numeric value. All operations assume a 2’s complement representation. • Short Integer — A signed 32-bit numeric value (double word). All operations assume a 2’s complement representation.
Page 293: C187-Supported Data Types
MATH COPROCESSING Word Magnitude Integer Short Magnitude Integer Long Integer Packed Decimal Short Biased Real Exponent Long Biased Exponent Real Temporary Biased Exponent Real NOTES: S = Sign bit (0 = positive, 1 = negative) d n = Decimal digit (two per byte) X = Bits have no significance;...
Page 294: C186 Modular Core Family/80C187 System Configuration
External Oscillator AD15:0 CLKOUT 80C186 Modular Core RESET BUSY ERROR PEREQ Figure 11-2. 80C186 Modular Core Family/80C187 System Configuration MATH COPROCESSING Latch 80C187 RESET NPWR NPRD BUSY ERROR PEREQ NPS1 NPS2 D15:0 A1529-0A 11-9...
Page 295: Clocking The 80C187
MATH COPROCESSING 11.4.1 Clocking the 80C187 The microprocessor and math coprocessor operate asynchronously, and their clock rates may dif- fer. The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input from the microprocessor’s CLKOUT pin.
Page 296: System Design Tips
MATH COPROCESSING Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with respect to the processor’s control pins. See “System Design Tips” for information on integrating the 80C187 into the overall system. 11.4.3 System Design Tips All 80C187 operations require that bus ready be asserted.
Page 297: C187 Configuration With A Partially Buffered Bus
MATH COPROCESSING External Oscillator AD15:0 CLKOUT 80C186 Modular Core RESET BUSY ERROR PEREQ DT/R Figure 11-3. 80C187 Configuration with a Partially Buffered Bus 11-12 Latch A15:0 80C187 RESET NPWR NPRD BUSY ERROR PEREQ NPS1 NPS2 Buffer D15:8 T OE Buffer D7:0 T OE D15:0...
Page 298: Exception Trapping
MATH COPROCESSING 11.4.4 Exception Trapping The 80C187 detects six error conditions that can occur during instruction execution. The 80C187 can apply default fix-ups or signal exceptions to the microprocessor’s ERROR pin. The processor tests ERROR at the beginning of numerics instructions, so it traps an exception on the next at- tempted numerics instruction after it occurs.
Page 299: C187 Exception Trapping Via Processor Interrupt Pin
MATH COPROCESSING 80C186 Modular Core Latch A19:A16 AD15:0 D15:0 D15:0 CMD1 CMD0 80C187 A19:0 NPS2 Figure 11-4. 80C187 Exception Trapping via Processor Interrupt Pin 11-14 ERROR RESET CS x INT x BUSY PEREQ CLKOUT NPWR NPRD NPS1 PEREQ BUSY ERROR RESET A1531-0A...
Page 300: Initialization Sequence For 80C187 Math Coprocessor
$mod186 name example_80C187_init ;FUNCTION: This function initializes the 80C187 numerics coprocessor. ;SYNTAX: extern unsigned char far 187_init(void); ;INPUTS: None ;OUTPUTS: unsigned char - 0000h -> False -> coprocessor not initialized ;NOTE: Parameters are passed on the stack as required by high-level languages.
Page 301: Floating Point Math Routine Using Fsincos
The results of the computation are the coordinates x and y expressed as 32-bit reals. ;NOTES: This routine is coded for Intel ASM86. It is not set up as an HLL-callable routine. This code assumes that the 80C187 has already been initialized.
Page 302 ONCE Mode...
Page 304: Entering/Leaving Once Mode
CHAPTER 12 ONCE MODE ONCE (pronounced “ahnce”) Mode provides the ability to three-state all output, bidirectional, or weakly held high/low pins except OSCOUT. To allow device operation with a crystal network, OSCOUT does not three-state. ONCE Mode electrically isolates the device from the rest of the board logic. This isolation allows a bed-of-nails tester to drive the device pins directly for more accurate and thorough testing.
Page 305: Entering/Leaving Once Mode
ONCE MODE All output, bidirectional, weakly held pins except OSCOUT NOTES: 1. Entering ONCE Mode. 2. Latching ONCE Mode. 3. Leaving ONCE Mode (assuming 2 occurred). Figure 12-1. Entering/Leaving ONCE Mode 12-2 A1532-0A...
Page 306 80C186 Instruction Set Additions and Extensions...
Page 308: A.1 80C186 Instruction Set Additions
The 80C186 Modular Core family instruction set differs from the original 8086/8088 instruction set in two ways. First, several instructions that were not available in the 8086/8088 instruction set have been added. Second, several 8086/8088 instructions have been enhanced for the 80C186 Modular Core family instruction set.
Page 309: A.1.2 String Instructions
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.1.2 String Instructions INS source_string, port INS (in string) performs block input from an I/O port to memory. The port address is placed in the DX register. The memory address is placed in the DI register. This instruction uses the ES segment register (which cannot be overridden).
Page 310: A-1 Formal Definition Of Enter
The following listing gives the formal definition of the ENTER instruction for all cases. LEVEL denotes the value of the second operand. Push BP Set a temporary value FRAME_PTR: = SP If LEVEL > 0 then Repeat (LEVEL - 1) times: BP:=BP - 2 Push the word pointed to by BP End Repeat...
Page 311: A-2 Variable Access In Nested Procedures
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Figure A-2. Variable Access in Nested Procedures The first ENTER, executed in the Main Program, allocates dynamic storage space for Main, but no pointers are copied. The only word in the display points to itself because no previous value exists to return to after LEAVE is executed (see Figure A-3).
Page 312: A-4 Stack Frame For Procedure A At Level 2
*BPA = BP Value for Procedure A Figure A-4. Stack Frame for Procedure A at Level 2 After Procedure A calls Procedure B, ENTER creates the display for Procedure B. The first word of the display points to the previous value of BP (BPA). The second word points to the value of BP for MAIN (BPM).
Page 313: A-5 Stack Frame For Procedure B At Level 3 Called From A
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Figure A-5. Stack Frame for Procedure B at Level 3 Called from A Old BP Display B Storage B Dynamic A1004-0A...
Page 314: A-6 Stack Frame For Procedure C At Level 3 Called From B
Figure A-6. Stack Frame for Procedure C at Level 3 Called from B LEAVE LEAVE reverses the action of the most recent ENTER instruction. It collapses the last stack frame created. First, LEAVE copies the current BP to the Stack Pointer, releasing the stack space allocated to the current procedure.
Page 315: A.2 80C186 Instruction Set Enhancements
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BOUND register, address BOUND verifies that the signed value in the specified register lies within specified limits. If the value does not lie within the bounds, an array bounds exception (type 5) occurs. BOUND is useful for checking array bounds before attempting to access an array element.
Page 316: A.2.2 Arithmetic Instructions
A.2.2 Arithmetic Instructions IMUL destination, source, data IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate op- erand. IMUL requires three operands. The first, destination, is the register where the result will be placed. The second, source, is the effective address of the multiplier. The source may be the same register as the destination, another register or a memory location.
Page 317: A.2.3.2 Rotate Instructions
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.3.2 Rotate Instructions ROL destination, count ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL has two operands. The first, destination, is the effective address to be rotated. The second, count, is an immediate byte value representing the number of rotations to be made.
Page 318 Input Synchronization...
Page 320: B.1 Why Synchronizers Are Required
Many input signals to an embedded processor are asynchronous. Asynchronous signals do not re- quire a specified setup or hold time to ensure the device does not incur a failure. However, asyn- chronous setup and hold times are specified in the data sheet to ensure recognition. Associated with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchro- nous signal and synchronizes it to the internal operating clock.
Page 321: B.2 Asynchronous Pins
As the sampling window gets smaller, the number of times an asynchro- nous transition occurs during the sampling window drops. ASYNCHRONOUS PINS The 80C186XL/80C188XL inputs that use the two-stage synchronization circuit are TMR IN 0, TMR IN 1, NMI, TEST/BUSY, INT3:0, HOLD, DRQ0 and DRQ1.
Page 322 Instruction Set Descriptions...
Page 324 INSTRUCTION SET DESCRIPTIONS This appendix provides reference information for the 80C186 Modular Core family instruction set. Tables C-1 through C-3 define the variables used in Table C-4, which lists the instructions with their descriptions and operations. Table C-1. Instruction Format Variables Variable dest A register or memory location that may contain data operated on by the instruction,...
Page 325 INSTRUCTION SET DESCRIPTIONS Table C-2. Instruction Operands Operand An 8- or 16-bit general register. reg16 An 16-bit general register. seg-reg A segment register. accum Register AX or AL immed A constant in the range 0–FFFFH. immed8 A constant in the range 0–FFH. An 8- or 16-bit memory location.
Page 326 Table C-3. Flag Bit Functions Name Auxiliary Flag: Set on carry from or borrow to the low order four bits of AL; cleared otherwise. Carry Flag: Set on high-order bit carry or borrow; cleared otherwise. Direction Flag: Causes string instructions to auto decrement the appropriate index register when set.
Page 327 INSTRUCTION SET DESCRIPTIONS Name Description ASCII Adjust for Addition: Changes the contents of register AL to a valid unpacked decimal number; the high-order half-byte is zeroed. Instruction Operands: none ASCII Adjust for Division: Modifies the numerator in AL before dividing two valid unpacked decimal operands so that the quotient produced by the division will be a valid unpacked decimal number.
Page 328 Table C-4. Instruction Set (Continued) Name Description ASCII Adjust for Subtraction: Corrects the result of a previous subtraction of two valid unpacked decimal operands (the destination operand must have been specified as register AL). Changes the content of AL to a valid unpacked decimal number;...
Page 329 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Addition: ADD dest , src Sums two operands, which may be bytes or words, replaces the destination operand. Both operands may be signed or unsigned binary numbers (see AAA and DAA). Instruction Operands: ADD reg, reg ADD reg, mem...
Page 330 Table C-4. Instruction Set (Continued) Name Description BOUND Detect Value Out of Range: BOUND dest , src Provides array bounds checking in hardware. The calculated array index is placed in one of the general purpose registers, and the upper and lower bounds of the array are placed in two consecutive memory locations.
Page 331 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Convert Byte to Word: Extends the sign of the byte in register AL throughout register AH. Use to produce a double-length (word) dividend from a byte prior to performing byte division. Instruction Operands: none Clear Carry flag:...
Page 332 Table C-4. Instruction Set (Continued) Name Description Clear Interrupt-enable Flag: Zeroes the interrupt-enable flag (IF). When the interrupt-enable flag is cleared, the 8086 and 8088 do not recognize an external interrupt request that appears on the INTR line; in other words maskable interrupts are disabled.
Page 333 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Compare: CMP dest , src Subtracts the source from the desti- nation, which may be bytes or words, but does not return the result. The operands are unchanged, but the flags are updated and can be tested by a subsequent conditional jump instruction.
Page 334 Table C-4. Instruction Set (Continued) Name Description Convert Word to Doubleword: Extends the sign of the word in register AX throughout register DX. Use to produce a double-length (doubleword) dividend from a word prior to performing word division. Instruction Operands: none Decimal Adjust for Addition: Corrects the result of previously...
Page 335 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Decrement: DEC dest Subtracts one from the destination operand. The operand may be a byte or a word and is treated as an unsigned binary number (see AAA and DAA). Instruction Operands: DEC reg DEC mem...
Page 336 Table C-4. Instruction Set (Continued) Name Description Divide: DIV src Performs an unsigned division of the accumulator (and its extension) by the source operand. If the source operand is a byte, it is divided into the two-byte dividend assumed to be in registers AL and AH. The byte quotient is returned in AL, and the byte remainder is returned in If the source operand is a word, it is...
Page 337 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description ENTER Procedure Entry: ENTER locals, levels Executes the calling sequence for a high-level language. It saves the current frame pointer in BP, copies the frame pointers from procedures below the current call (to allow access to local variables in these procedures) and allocates space on the stack for the local variables of the current...
Page 338 Table C-4. Instruction Set (Continued) Name Description Halt: Causes the CPU to enter the halt state. The processor leaves the halt state upon activation of the RESET line, upon receipt of a non-maskable interrupt request on NMI, or upon receipt of a maskable interrupt request on INTR (if interrupts are enabled).
Page 339 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description IDIV Integer Divide: IDIV src Performs a signed division of the accumulator (and its extension) by the source operand. If the source operand is a byte, it is divided into the double- length dividend assumed to be in registers AL and AH;...
Page 340 Table C-4. Instruction Set (Continued) Name Description IMUL Integer Multiply: IMUL src Performs a signed multiplication of the source operand and the accumulator. If the source is a byte, then it is multiplied by register AL, and the double-length result is returned in AH and AL.
Page 341 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Increment: INC dest Adds one to the destination operand. The operand may be byte or a word and is treated as an unsigned binary number (see AAA and DAA). Instruction Operands: INC reg INC mem In String:...
Page 342 Table C-4. Instruction Set (Continued) Name Description Interrupt: INT interrupt-type Activates the interrupt procedure specified by the interrupt-type operand. Decrements the stack pointer by two, pushes the flags onto the stack, and clears the trap (TF) and interrupt-enable (IF) flags to disable single-step and maskable interrupts.
Page 343 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description INTO Interrupt on Overflow: INTO Generates a software interrupt if the overflow flag (OF) is set; otherwise control proceeds to the following instruction without activating an interrupt procedure. INTO addresses the target interrupt procedure (its type is 4) through the interrupt pointer at location 10H;...
Page 344 Table C-4. Instruction Set (Continued) Name Description Jump on Above or Equal: Jump on Not Below: JAE disp8 JNB disp8 Transfers control to the target location if the tested condition (CF = 0) is true. Instruction Operands: JAE short-label JNB short-label Jump on Below: JNAE Jump on Not Above or Equal:...
Page 345 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description JCXZ Jump if CX Zero: JCXZ disp8 Transfers control to the target location if CX is 0. Useful at the beginning of a loop to bypass the loop if CX has a zero value, i.e., to execute the loop zero times.
Page 346 Table C-4. Instruction Set (Continued) Name Description Jump on Less Than: JNGE Jump on Not Greater Than or Equal: JL disp8 JNGE disp8 Transfers control to the target location if the condition tested (SF OF) is true. Instruction Operands: JL short-label JNGE short-label Jump on Less Than or Equal: Jump on Not Greater Than:...
Page 347 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Jump on Not Equal: Jump on Not Zero: JNE disp8 JNZ disp8 Transfers control to the target location if the tested condition (ZF = 0) is true. Instruction Operands: JNE short-label JNZ short-label Jump on Not Overflow: JNO disp8...
Page 348 Table C-4. Instruction Set (Continued) Name Description Jump on Overflow: JO disp8 Transfers control to the target location if the tested condition (OF = 1) is true. Instruction Operands: JO short-label Jump on Parity: Jump on Parity Equal: JP disp8 JPE disp8 Transfers control to the target location if the tested condition (PF = 1) is true.
Page 349 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Load Pointer Using DS: LDS dest, src Transfers a 32-bit pointer variable from the source operand, which must be a memory operand, to the destination operand and register DS. The offset word of the pointer is transferred to the destination operand, which may be any 16-bit general register.
Page 350 Table C-4. Instruction Set (Continued) Name Description Load Pointer Using ES: LES dest, src Transfers a 32-bit pointer variable from the source operand to the destination operand and register ES. The offset word of the pointer is transferred to the destination operand.
Page 351 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description LODS Load String (Byte or Word): LODS src-string Transfers the byte or word string element addressed by SI to register AL or AX and updates SI to point to the next element in the string.
Page 352 Table C-4. Instruction Set (Continued) Name Description LOOPNE Loop While Not Equal: LOOPNZ Loop While Not Zero: LOOPNE disp8 LOOPNZ disp8 Decrements CX by 1 and transfers control to the target location if CX is not 0 and if ZF is clear; otherwise the next sequential instruction is executed.
Page 353 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description MOVS Move String: MOVS dest-string, src-string Transfers a byte or a word from the source string (addressed by SI) to the destination string (addressed by DI) and updates SI and DI to point to the next string element.
Page 354 Table C-4. Instruction Set (Continued) Name Description Negate: NEG dest Subtracts the destination operand, which may be a byte or a word, from 0 and returns the result to the desti- nation. This forms the two's complement of the number, effectively reversing the sign of an integer.
Page 355 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Logical OR: OR dest,src Performs the logical "inclusive or" of the two operands (bytes or words) and returns the result to the destination operand. A bit in the result is set if either or both corresponding bits in the original operands are set;...
Page 356 Table C-4. Instruction Set (Continued) Name Description OUTS Out String: OUTS port, src_string Performs block output from memory to an I/O port. The port address is placed in the DX register. The memory address is placed in the SI register. This instruction uses the DS segment register, but this may be changed with a segment override instruction.
Page 357 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description POPA Pop All: POPA Pops all data, pointer, and index registers off of the stack. The SP value popped is discarded. Instruction Operands: none POPF Pop Flags: POPF Transfers specific bits from the word at the current top of stack (pointed to by register SP) into the 8086/8088 flags, replacing whatever values the flags...
Page 358 Table C-4. Instruction Set (Continued) Name Description PUSHA Push All: PUSHA Pushes all data, pointer, and index registers onto the stack . The order in which the registers are saved is: AX, CX, DX, BX, SP, BP, SI, and DI. The SP value pushed is the SP value before the first register (AX) is pushed.
Page 359 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Rotate Through Carry Left: RCL dest, count Rotates the bits in the byte or word destination operand to the left by the number of bits specified in the count operand. The carry flag (CF) is treated as "part of"...
Page 360 Table C-4. Instruction Set (Continued) Name Description Repeat: REPE Repeat While Equal: REPZ Repeat While Zero: REPNE Repeat While Not Equal: REPNZ Repeat While Not Zero: Controls subsequent string instruction repetition. The different mnemonics are provided to improve program clarity. REP is used in conjunction with the MOVS (Move String) and STOS (Store String) instructions and is interpreted...
Page 361 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Return: RET optional-pop-value Transfers control from a procedure back to the instruction following the CALL that activated the procedure. The assembler generates an intra- segment RET if the programmer has defined the procedure near, or an intersegment RET if the procedure has been defined as far.
Page 362 Table C-4. Instruction Set (Continued) Name Description Rotate Right: ROR dest, count Operates similar to ROL except that the bits in the destination byte or word are rotated right instead of left. Instruction Operands: ROR reg, n ROR mem, n ROR reg, CL ROR mem, CL SAHF...
Page 363 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Shift Logical Left: Shift Arithmetic Left: SHL dest, count SAL dest, count Shifts the destination byte or word left by the number of bits specified in the count operand. Zeros are shifted in on the right.
Page 364 Table C-4. Instruction Set (Continued) Name Description Subtract With Borrow: SBB dest, src Subtracts the source from the desti- nation, subtracts one if CF is set, and returns the result to the destination operand. Both operands may be bytes or words. Both operands may be signed or unsigned binary numbers (see AAS and DAS) Instruction Operands:...
Page 365 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description SCAS Scan String: SCAS dest-string Subtracts the destination string element (byte or word) addressed by DI from the content of AL (byte string) or AX (word string) and updates the flags, but does not alter the destination string or the accumulator.
Page 366 Table C-4. Instruction Set (Continued) Name Description Shift Logical Right: SHR dest, src Shifts the bits in the destination operand (byte or word) to the right by the number of bits specified in the count operand. Zeros are shifted in on the left.
Page 367 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description Set Interrupt-enable Flag: Sets IF to 1, enabling processor recognition of maskable interrupt requests appearing on the INTR line. Note however, that a pending interrupt will not actually be recognized until the instruction following STI has executed.
Page 368 Table C-4. Instruction Set (Continued) Name Description Subtract: SUB dest, src The source operand is subtracted from the destination operand, and the result replaces the destination operand. The operands may be bytes or words. Both operands may be signed or unsigned binary numbers (see AAS and DAS).
Page 369 INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description WAIT Wait: WAIT Causes the CPU to enter the wait state while its test line is not active. Instruction Operands: none XCHG Exchange: XCHG dest, src Switches the contents of the source and destination operands (bytes or words).
Page 370 Table C-4. Instruction Set (Continued) Name Description XLAT Translate: XLAT translate-table Replaces a byte in the AL register with a byte from a 256-byte, user-coded translation table. Register BX is assumed to point to the beginning of the table. The byte in AL is used as an index into the table and is replaced by the byte at the offset in the table corre- sponding to AL's binary value.
Page 372 Instruction Set Opcodes and Clock Cycles...
Page 374 This appendix provides reference information for the 80C186 Modular Core family instruction set. Table D-1 defines the variables used in Table D-2, which lists the instructions with their for- mats and execution times. Table D-3 is a guide for decoding machine instructions. Table D-4 is a guide for encoding instruction mnemonics, and Table D-5 defines Table D-4 abbreviations.
Page 375 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary Function DATA TRANSFER INSTRUCTIONS MOV = Move register to register/memory 1 0 0 0 1 0 0 w register/memory to register 1 0 0 0 1 0 1 w immediate to register/memory 1 1 0 0 0 1 1 w immediate to register...
Page 376 Table D-2. Instruction Set Summary (Continued) Function DATA TRANSFER INSTRUCTIONS (Continued) LEA = Load EA to register 1 0 0 0 1 1 0 1 LDS = Load pointer to DS 1 1 0 0 0 1 0 1 LES = Load pointer to ES 1 1 0 0 0 1 0 0 ENTER = Build stack frame 1 1 0 0 1 0 0 0...
Page 377 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function ARITHMETIC INSTRUCTIONS (Continued) SUB = Subtract reg/memory with register to either 0 0 1 0 1 0 d w immediate from register/memory 1 0 0 0 0 0 s w immediate from accumulator 0 0 0 1 1 1 0 w SBB = Subtract with borrow...
Page 378 Table D-2. Instruction Set Summary (Continued) Function ARITHMETIC INSTRUCTIONS (Continued) AAM = ASCII adjust for multiply 1 1 0 1 0 1 0 0 DIV = Divide (unsigned) 1 1 1 1 0 1 1 w register-byte register-word memory-byte memory-word IDIV = Integer divide (signed) 1 1 1 1 0 1 1 w register-byte...
Page 379 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function BIT MANIPULATION INSTRUCTIONS (Continued) TEST= And function to flags, no result register/memory and register 1 0 0 0 0 1 0 w immediate data and register/memory 1 1 1 1 0 1 1 w immediate data and accumulator 1 0 1 0 1 0 0 w Shifts/Rotates...
Page 380 Table D-2. Instruction Set Summary (Continued) Function PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers — jump if: JE/JZ= equal/zero 0 1 1 1 0 1 0 0 JL/JNGE = less/not greater or equal 0 1 1 1 1 1 0 0 JLE/JNG = less or equal/not greater 0 1 1 1 1 1 1 0 JB/JNAE = below/not above or equal 0 1 1 1 0 0 1 0...
Page 381 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function PROGRAM TRANSFER INSTRUCTIONS (Continued) RET = Return from procedure within segment 1 1 0 0 0 0 1 1 within segment adding immed to SP 1 1 0 0 0 0 1 0 intersegment 1 1 0 0 1 0 1 1 intersegment adding immed to SP...
Page 382 Table D-2. Instruction Set Summary (Continued) Function PROCESSOR CONTROL INSTRUCTIONS CLC = Clear carry 1 1 1 1 1 0 0 0 CMC = Complement carry 1 1 1 1 0 1 0 1 STC = Set carry 1 1 1 1 1 0 0 1 CLD = Clear direction 1 1 1 1 1 1 0 0 STD = Set direction...
Page 383 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 0000 1001 mod reg r/m 0000 1010 mod reg r/m 0000 1011 mod reg r/m 0000 1100 data-8 0000 1101 data-lo 0000 1110 0000 1111 0001 0000 mod reg r/m...
Page 384 Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 0010 1110 0010 1111 0011 0000 mod reg r/m (disp-lo),(disp-hi) 0011 0001 mod reg r/m (disp-lo),(disp-hi) 0011 0010 mod reg r/m (disp-lo),(disp-hi) 0011 0011 mod reg r/m (disp-lo),(disp-hi) 0011 0100 data-8 0011 0101...
Page 385 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 0101 0011 0101 0100 0101 0101 0101 0110 0101 0111 0101 1000 0101 1001 0101 1010 0101 1011 0101 1100 0101 1101 0101 1110 0101 1111 0110 0000...
Page 386 Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 0111 1110 IP-inc-8 0111 1111 IP-inc-8 1000 0000 mod 000 r/m (disp-lo),(disp-hi), data-8 mod 001 r/m (disp-lo),(disp-hi), data-8 mod 010 r/m (disp-lo),(disp-hi), data-8 mod 011 r/m (disp-lo),(disp-hi), data-8 mod 100 r/m (disp-lo),(disp-hi), data-8 mod 101 r/m...
Page 387 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 1000 0111 mod reg r/m 1000 0100 mod reg r/m 1000 1001 mod reg r/m 1000 1010 mod reg r/m 1000 1011 mod reg r/m 1000 1100 mod OSR r/m...
Page 388 Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 1010 1010 1010 1011 1010 1100 1010 1101 1010 1110 1010 1111 1011 0000 data-8 1011 0001 data-8 1011 0010 data-8 1011 0011 data-8 1011 0100 data-8 1011 0101 data-8 1011 0110 data-8...
Page 389 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary mod 111 r/m 1100 0010 data-lo 1100 0011 1100 0100 mod reg r/m 1100 0101 mod reg r/m 1100 0110 mod 000 r/m mod 001 r/m mod 010 r/m mod 011 r/m...
Page 390 Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 1101 0001 mod 000 r/m (disp-lo),(disp-hi) mod 001 r/m (disp-lo),(disp-hi) 1101 0001 mod 010 r/m (disp-lo),(disp-hi) mod 011 r/m (disp-lo),(disp-hi) mod 100 r/m (disp-lo),(disp-hi) mod 101 r/m (disp-lo),(disp-hi) mod 110 r/m (disp-lo),(disp-hi) mod 111 r/m...
Page 391 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 1110 0001 IP-inc-8 1110 0010 IP-inc-8 1110 0011 IP-inc-8 1110 0100 data-8 1110 0101 data-8 1110 0110 data-8 1110 0111 data-8 1110 1000 IP-inc-lo 1110 1001 IP-inc-lo...
Page 392 Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Binary 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 mod 000 r/m (disp-lo),(disp-hi) mod 001 r/m (disp-lo),(disp-hi) mod 010 r/m 1111 1110 mod 011 r/m mod 100 r/m mod 101 r/m mod 110 r/m...
Page 393 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4. Mnemonic Encoding Matrix (Left Half) b,f,r/m w,f,r/m b,f,r/m w,f,r/m b,f,r/m w,f,r/m b,f,r/m w,f,r/m PUSH PUSH PUSHA POPA Immed Immed b,r/m w,r/m XCHG (XCHG) m AL m AX i AL i CL Shift Shift Shift Shift...
Page 394 Table D-4. Mnemonic Encoding Matrix (Right Half) b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,f,r/m w,f,r/m b,t,r/m w,t,r/m PUSH IMUL PUSH b,f,r/m w,f,r/m b,t,r/m w,t,r/m CALL WAIT TEST TEST STOS STOS b,ia w,ia i AX i CX i DX i BX...
Page 395 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-5. Abbreviations for Mnemonic Encoding Matrix Abbr Definition Abbr byte operation immediate to accumulator direct indirect from CPU register immediate byte, sign extended immediate long (intersegment) Byte 2 Immed mod 000 r/m mod 001 r/m mod 010 r/m mod 011 r/m mod 100 r/m...
Page 396 Index...
Page 398 80C187 Math Coprocessor, 10-2–10-8 accessing, 10-10–10-11 arithmetic instructions, 10-3–10-4 bus cycles, 10-11 clocking, 10-10 code examples, 10-13–10-16 comparison instructions, 10-5 constant instructions, 10-6 data transfer instructions, 10-3 data types, 10-7–10-8 design considerations, 10-10–10-11 example floating point routine, 10-16 exceptions, 10-13 I/O port assignments, 10-10 initialization example, 10-13–10-16 instruction set, 10-2...
Page 399 INDEX and chip-selects, 6-5 HALT state, exiting, 3-30 idle states, 3-18 instruction prefetch, 3-20 interrupt acknowledge (INTA) cycles, 3-6, 3-25–3-26, 8-9 and chip-selects, 6-5 interrupt acknowledge cycles, 8-29 operation, 3-7–3-20 priorities, 3-44–3-45, 7-2 read cycles, 3-20–3-21 refresh cycles, 3-22, 7-4, 7-5 control signals, 7-5, 7-6 during HOLD, 3-41–3-43, 7-12–7-13 wait states, 3-13–3-18...
Page 400 Data sheets, obtaining from BBS, 1-5 Data transfers, 3-1–3-6 instructions, 2-18 PCB considerations, 4-5 PSW flag storage formats, 2-19 See also Bus cycles Data types, 2-37–2-38 DI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34 Digital one-shot, code example, 9-17–9-23 Direct Memory Access (DMA) Unit, 10-1–10-27 and BIU, 10-8 and CSU, 10-8...
Page 401 INDEX Fault exceptions, 2-43 FaxBack service, 1-4 F-Bus and PCB, 4-5 operation, 4-5 Flags‚ See Processor Status Word (PSW) Floating Point, defined, 2-37 HALT bus cycle‚ See Bus cycles HOLD/HLDA protocol‚ See Bus hold protocol Hypertext manuals, obtaining from BBS, 1-5 I/O devices interfacing with, 3-6–3-7 memory-mapped, 3-6...
Page 402 maskable, 2-43 masking, 8-3, 8-12, 8-16 priority-based, 8-17 multiplexed, 8-7 nesting, 8-4 NMI, 2-42 nonmaskable, 2-45 overview, 8-1, 8-2 priority, 2-46–2-49, 8-3 default, 8-3 resolution, 8-5, 8-6 processing, 2-39–2-42 reserved, 2-39 response time, 2-46 selecting edge- or level-triggering, 8-12 slave mode sources, 8-25 software, 2-45 timer interrupts, 9-16 types, 8-9, 8-26, 8-27...
Page 403 INDEX Polling, 8-1, 8-9 POPA instruction, A-1 Power consumption‚ reducing, 3-28 Power management, 5-10–5-14 Power management modes and HALT bus cycles, 3-30 Powerdown mode, 7-2 Power-Save mode, 5-11–5-14, 7-2 and DRAM refresh rate, 5-13 and refresh interval, 7-7 control register, 5-12 entering, 5-11 exiting, 5-13 initialization code, 5-13–5-14...
Page 404 SI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34 Sign Flag (SF), 2-7, 2-9 Single-step trap (Type 1 exception), 2-43 Software code example 80C187 floating-point routine, 10-16 80C187 initialization, 10-13–10-15 digital one-shot, 9-17–9-23 DMA initialization, 10-22–10-27 ICU initialization, 8-31 real-time clock, 9-17–9-19 square-wave generator, 9-17–9-22 TCU configurations, 9-17–9-23...
Page 405 INDEX and PCB accesses, 4-4 and READY input, 3-13 Word integer, defined, 10-7 World Wide Web, 1-6 Write bus cycle, 3-22 Zero Flag (ZF), 2-7, 2-9, 2-23 Index-8...

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80c188xl

Intel 80C186XL User Manual

Chapter 1 Introduction

Chapter 2 Overview of the 80C186 Family Architecture

Chapter 3

Chapter 4

Chapter 5 Clock Generation

Chapter 6

Examples

Chapter 7

Chapter 8 Master Mode

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