Intel 82496 CACHE CONTROLLER User Manual page 332

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HARDWARE INTERFACE
5.2.2.137.
TOI
TDI Test Data Input
Receives serial test instructions and data.
Input to Pentium processor (pin T21), 82496 Cache Controller (pin P04), and
82491 Cache SRAM (pin 2)
Synchronous to TCK
Pentium processor, 82496 Cache Controller, 82491 Cache SRAM internal Pull-ups
Signal Description
TDI is the serial input used to shift IT AG instructions and data into the component. The
shifting of instructions and data occurs during the SHIFT-IR and SHIFf-DR TAP controller
states, respectively. These states are selected using the TMS signal as described in the
testability chapter.
An internal pull up resistor is provided on TDI to ensure a known logic state if an open circuit
occurs on the TDI path. Note that when the value I is continuously shifted into the instruction
register, the BYPASS instruction is selected.
When Sampled
TDI is sampled on the rising edge of TCK, and during the SHIFT-IR and SHIFT-DR states.
During all other TAP controller states, TDI is a "don't care".
Relation to Other Signals
Pin Symbol Relation to Other Signals
TCK
TDI is only sampled when TMS and TCK have been used to select the SHIFT-IR
or SHIFT-DR states in the TAP controller.
TMS and TDI are sampled on the rising edge of TCK.
TMS TDI is only sampled when TMS and TCK have been used to select the SHIFT-IR
or SHIFT-DR states in the TAP controller.
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