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Intel VC820 - Desktop Board Motherboard Design Manual

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Intel
820 Chipset
Design Guide
July 2000
Order Number:
290631-004

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   Summary of Contents for Intel VC820 - Desktop Board Motherboard

  • Page 1

    ® Intel 820 Chipset Design Guide July 2000 Order Number: 290631-004...

  • Page 2

    Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    1.4.6 AC’97 .....................1-10 1.4.7 Low Pin Count (LPC) Interface ............1-11 Layout/Routing Guidelines..................2-1 General Recommendations ................2-1 Component Quadrant Layout................2-1 ® Intel 820 Chipset Component Placement ...........2-3 Core Chipset Routing Recommendations.............2-4 Source Synchronous Strobing ..............2-5 Direct Rambus* Interface................2-7 2.6.1 Stackup ....................2-8 2.6.2 Direct Rambus* Layout Guidelines ..........2-8...

  • Page 4

    3.3.3 Cross-talk Theory ................3-16 More Details and Insight ................3-19 3.4.1 Textbook Timing Equations ............3-19 3.4.2 Effective Impedance and Tolerance/Variation .......3-20 3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling ..............3-20 3.4.4 Clock Routing ................3-23 ® Intel 820 Chipset Design Guide...

  • Page 5

    6.1.3 64/72Mbit RDRAM Excessive Power Consumption ......6-5 Power Plane Splits..................6-7 Thermal Design Power .................6-7 ® Glue Chip 3 (Intel 820 Chipset Glue Chip) ..........6-8 Reference Design Schematics: Uni-Processor............A-1 Reference Design Feature Set ..............A-1 Reference Design Schematics: Dual-Processor............B-1 Reference Design Feature Set ..............

  • Page 6

    Figures ® Intel 820 Chipset Platform Performance Desktop Block Diagram ....1-5 ® Intel 820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge)...................1-6 ® Intel 820 Chipset Platform Dual-Processor Performance Desktop Block Diagram ....................1-7 AC’97 Connections ..................1-11 MCH 324-uBGA Quadrant Layout (Top View)..........2-2 ICH 241-uBGA Quadrant Layout (Top View)..........2-2...

  • Page 7

    3-11 Overdrive Region and V Guardband.............3-25 3-12 Rising Edge Flight Time Measurement............3-25 ® Intel 820 Chipset Platform Clock Distribution ..........4-2 ® Intel 820 Chipset Clock Routing Guidelines ..........4-4 CK133 to DRCG Routing Diagram ...............4-6 MCH to DRCG Routing Diagram ..............4-7 Direct Rambus* Clock Routing Dimensions..........4-7...

  • Page 8

    Segment Descriptions and Lengths for Figure 2-36 ........2-46 2-13 Processor and 82820 MCH Connection Checklist........2-49 ® 2-14 Bus Request Connection Scheme for DP Intel 820 Chipset Designs..2-52 2-15 ICH Codec Options..................2-61 2-16 AC'97 SDIN Pulldown Resistors ..............2-63 AGTL+ Parameters for Example Calculations ..........3-6 Example T Calculations for 133 MHz Bus ........3-7...

  • Page 9: Revision History

    • Updated the text descriptions in the two paragraphs in Section 4.2.3, “MCH to DRCG”. -003 January 2000 • Updated the first paragraph in Section 2.6.2.5, “RSL Signal Layer Alternation“. -004 • Minor edits for clarity July 2000 ® Intel 820 Chipset Design Guide...

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    This page is intentionally left blank. ® Intel 820 Chipset Design Guide...

  • Page 11: Introduction

    Introduction...

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  • Page 13: About This Design Guide

    The Intel board schematics in Appendix A (uni-processor) and Appendix B (dual-processor) can be used as references for board designers. A feature list is provided at the beginning of each appendix.

  • Page 14: References

    By increasing memory bandwidth to 1.6 GB/s through the use of 400 MHz Direct ® RDRAM and increasing graphics bandwidth to 1 GB/s through the use of AGP 4X, the Intel chipset delivers the data throughput necessary to take advantage of the high performance provided by the powerful Pentium III processor.

  • Page 15: Chipset Components

    LPC interface controller, FWH Flash BIOS interface controller, PCI interface controller, AC’97 ® digital controller and a hub interface for communication with the MCH. The Intel 820 chipset provides the data buffering and interface arbitration required to ensure that system interfaces operate efficiently and provide the system bandwidth necessary to obtain peak performance with the Pentium III processor.

  • Page 16: Bandwidth Summary

    ISA Bridge (82380AB) ® For legacy needs, ISA support is an optional feature of the Intel 820 chipset. Implementations that ® require ISA support can benefit from the enhancements of the Intel 820 chipset while “ISA-less”...

  • Page 17: System Configuration

    Introduction 1.3.3 System Configuration ® The following figures show typical platform configurations using the Intel 820 chipset. ® Figure 1-1. Intel 820 Chipset Platform Performance Desktop Block Diagram Processor 82820 4X AGP Memory AGP 2.0 Main Graphics Controller Hub Memory...

  • Page 18

    Introduction ® Figure 1-2. Intel 820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge) Processor 82820 4X AGP Memory AGP 2.0 Main Controller Hub Graphics Memory Controller (MCH) Hub Interface PCI Slots 4 IDE Drives PCI Bus 2 USB Ports...

  • Page 19: 820 Chipset Platform Dual-processor Performance Desktop Block Diagram

    Introduction ® Figure 1-3. Intel 820 Chipset Platform Dual-Processor Performance Desktop Block Diagram Processor Processor Optional 2-Way/MP 82820 4X AGP Memory AGP 2.0 Main Controller Hub Graphics Memory Controller (MCH) Hub Interface PCI Slots 4 IDE Drives PCI Bus 2 USB Ports...

  • Page 20: Platform Initiatives

    Streaming SIMD Extensions The Pentium III processor provides 70 new Streaming SIMD (single instruction, multiple data) Extensions. The Pentium III new extensions are floating point SIMD extensions. Intel MMX™ technology provides integer SIMD extensions. The Pentium III processor new extensions complement the Intel MMX™...

  • Page 21: Manageability

    1.4.5 Manageability ® The Intel 820 chipset platform integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.

  • Page 22

    820 chipset platform. In addition, an AC’97 soft modem can be implemented ® with the use of a modem codec. Several system options exist when implementing AC’97. Intel 820 chipset’s integrated digital link allows two external codecs to be connected to the ICH. The...

  • Page 23: Ac'97 Connections

    1.4.7 Low Pin Count (LPC) Interface ® In the Intel 820 chipset platform, the super I/O component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost super I/O designs. The LPC super I/O component requires the same feature set as traditional super I/O components.

  • Page 24

    Introduction This page is intentionally left blank ® 1-12 Intel 820 Chipset Design Guide...

  • Page 25

    Layout and Routing Guidelines...

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    This page is intentionally left blank.

  • Page 27: Layout/routing Guidelines

    Layout/Routing Guidelines Layout/Routing Guidelines ® This chapter documents motherboard layout and routing guidelines for Intel 820 chipset based systems. This section does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. Caution: If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design.

  • Page 28: Mch 324-ubga Quadrant Layout (top View)

    Layout/Routing Guidelines Figure 2-1. MCH 324-uBGA Quadrant Layout (Top View) System Bus (324-uBGA) Direct RDRAM Figure 2-2. ICH 241-uBGA Quadrant Layout (Top View) Pin #1 Corner Processor Hub Interface 241 uBGA AC'97, SMBus ® Intel 820 Chipset Design Guide...

  • Page 29: Intel ® 820 Chipset Component Placement

    Notes: ® Figure 2-3 The ATX placements and layouts shown in recommended for single (UP) Intel chipset based system design. 2. The trace length limitation between critical connections will be addressed later in this document. The figure is for reference only.

  • Page 30: Core Chipset Routing Recommendations

    Layout/Routing Guidelines Core Chipset Routing Recommendations Figure 2-4 Figure 2-5 show MCH core routing examples. Figure 2-4. Primary Side MCH Core Routing Example (ATX) ® Intel 820 Chipset Design Guide...

  • Page 31: Source Synchronous Strobing

    (T ) on maximum bus frequency. prop A source synchronous strobed interface uses strobe signals (instead of the clock) to indicate that data is valid. Refer to Figure 2-6 for an example. ® Intel 820 Chipset Design Guide...

  • Page 32: Data Strobing Example

    In this example, the lower address signals (AD[15:0]) are sampled on the rising and falling edges of AD_STB0, while the upper address signals (AD[31:16]) are sampled on the rising and falling edges of AD_STB1. ® Intel 820 Chipset Design Guide...

  • Page 33: Direct Rambus* Interface

    RDRAMs, are incorporated into the design to create a uniform bus structure that can support up to 33 devices (including the MCH) running at 800 MegaTransfers/second (MT/s). ® Intel 820 Chipset Design Guide...

  • Page 34: Stackup

    Direct RDRAM interface to work properly. Maintaining 28 Ω (±10%) loaded impedance for every RSL (Direct Rambus* Signaling Level) signal has changed the requirements for trace width and ® prepreg thickness for the Intel 820 chipset platform (refer to Section 5.3, “Stackup Requirement”...

  • Page 35: Rsl Routing Dimensions

    RSL signals. Figure 2-10. RSL Routing Diagram 18 mils RSL Signal Trace 6 mils Space 10 mils Ground 6 mils Space 18 mils RSL Signal Trace 6 mils Space 10 mils Ground Space 6 mils ® Intel 820 Chipset Design Guide...

  • Page 36: Primary Side Rsl Breakout Example

    RSL breakout and route. Figure 2-11. Primary Side RSL Breakout Example Ground Flood (Shaded area) 18 mil clock traces when not 14:6 14 on 6 Differential clock pair Neckdown for BJT Neckdown to pass vias ® 2-10 Intel 820 Chipset Design Guide...

  • Page 37: Secondary Side Rsl Breakout Example

    The Vterm power island should be at LEAST 50 mils wide. This voltage does not need to be supplied during suspend-to-RAM. Figure 2-13. Direct RDRAM Termination Terminator R-packs RSL Signals Vterm ® Intel 820 Chipset Design Guide 2-11...

  • Page 38: Direct Rambus* Termination Example

    Note: It is necessary to compensate for the slight difference in electrical characteristics between a dummy via and a real via. Refer to Section 2.6.2.7, “VIA Compensation” on page 2-23 for more information on Via Compensation. Figure 2-14. Direct Rambus* Termination Example 2 GND VIAS / Capacitor ® 2-12 Intel 820 Chipset Design Guide...

  • Page 39: Incorrect Direct Rambus* Ground Plane Referencing

    The ground reference island under the RSL signals MUST be connected to the ground pins on the RIMM connector and the ground vias used to connect the ground isolation on the 1 and 4 layers. ® Intel 820 Chipset Design Guide 2-13...

  • Page 40

    Based on the stackup requirement in Section 5.3, “Stackup Requirement” on page 5-1 the copper tab area should be 2800 to 3600 sq mils. Different stackups require different copper tab areas. Table 2-3 shows example copper tab areas. ® 2-14 Intel 820 Chipset Design Guide...

  • Page 41: Copper Tab Area Calculation

    The following figures show a routing example of tab compensation capacitors. Note that ground floods around the RIMM pins must not be interrupted by the capacitor tabs, and they must be connected to avoid discontinuity in the ground plane as shown. ® Intel 820 Chipset Design Guide 2-15...

  • Page 42: Connector Compensation Example

    Layout/Routing Guidelines Figure 2-17. Connector Compensation Example ® 2-16 Intel 820 Chipset Design Guide...

  • Page 43

    Layout/Routing Guidelines Figure 2-18. Section A , Top Layer Outer C-tab Inner C-tab NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity ® Intel 820 Chipset Design Guide 2-17...

  • Page 44

    Layout/Routing Guidelines Figure 2-19. Section A , Bottom Layer NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity ® 2-18 Intel 820 Chipset Design Guide...

  • Page 45

    Layout/Routing Guidelines Figure 2-20. Section B , Top Layer NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity ® Intel 820 Chipset Design Guide 2-19...

  • Page 46: Bottom Layer

    MCH to the first RIMM socket, it must be routed on the primary layer from the first RIMM to the second RIMM as shown in Figure 2-22 (signal A). Signals to the termination resistors can be routed on either layer from the last RIMM. ® 2-20 Intel 820 Chipset Design Guide...

  • Page 47: Rsl Signal Layer Alternation

    ±10mil of a nominal length). The Nominal RSL Length is an arbitrary length (within the limits of the routing guidelines) to which all the RSL signals will be matched (within 10 mils). ALL RSL signals must meet the following equation. ® Intel 820 Chipset Design Guide 2-21...

  • Page 48: Rdram Trace Length Matching Example

    L1 + L3 = Nominal RSL Length ±10 mils L2 + L4 = Nominal RSL Length ±10 mils ® ® NOTE: Refer to the Intel 820 Chipset: Intel 82820 Memory Controller Hub (MCH) Datasheet for component package dimensions. The RDRAM clocks (CTM, CTM#, CFM and CFM#) must be longer than the RDRAM signals due to their increased trace velocity (because they are routed as a differential pair).

  • Page 49: Dummy" Via Vs. Real "via

    2.6.2.8 Length Matching & Via Compensation Example Table 2-5 can be used to ensure that the RSL signals are the correct length. Note: 2000 mils was chosen as an EXAMPLE Nominal RSL Length. ® Intel 820 Chipset Design Guide 2-23...

  • Page 50: Line Matching And Via Compensation Example

    8. Formula B max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil + 25 mil 9. Formula C: Motherboard Trace = (Nominal RSL Length - Package Dimension) * 1.021 10.Formula D: Motherboard Trace = (Nominal RSL Length - Package Dimension + 25 mil) * 1.021 ® 2-24 Intel 820 Chipset Design Guide...

  • Page 51: Direct Rambus* Reference Voltage

    MCH. The resistors must be 91 Ω pullup and 39 Ω pulldown; they also must 2% or better for S3 • mode reliability. The trace impedances remain 28 Ω. ® Intel 820 Chipset Design Guide 2-25...

  • Page 52: High-speed Cmos Termination

    2.6.4.2 Suspend-to-RAM Shunt Transistor ® When an Intel 820 chipset system enters or exits Suspend-to-RAM, power will be ramping to the MCH (i.e., it will be powering-up or powering-down). When power is ramping, the state of the MCH outputs is not guaranteed. Therefore, the MCH could drive the CMOS signals and issue CMOS commands.

  • Page 53: Rdram Cmos Shunt Transistor

    Figure 2-28. RDRAM CMOS Shunt Transistor 18 mils 18 mils 5 mils wide wide wide 175 mils 175 mils VCC5SBY 2N3904 PWROK 2N3904 5 mils wide 18 mils 18 mils wide wide mils mils 2N3904 ® Intel 820 Chipset Design Guide 2-27...

  • Page 54: Direct Rambus* Clock Routing

    2.6.5 Direct Rambus Clock Routing ® Refer to Chapter 4, “Clocking” for Intel 820 chipset platform Direct Rambus clock routing guidelines. 2.6.6 Direct Rambus* Design Checklist Use the following checklist as a final check to ensure the motherboard incorporates solid design practices.

  • Page 55

    (e.g., the RSL signals on the 4 layer can not be routed directly below the ground isolation split on the 3 layer) — Uniform ground isolation flood is exactly 6 mils from the RSL signals at all times ® Intel 820 Chipset Design Guide 2-29...

  • Page 56

    — All signals must be length matched within ±10 mils of the Nominal RSL Length (note: ® use the table in the Intel 820 chipset: 82820 Memory Controller Hub (MCH) Datasheet to verify trace lengths). Ensure that signals with a dummy via are compensated correctly.

  • Page 57: Agp 2.0

    AGP Interface Specification, ® Revision 2.0. The Intel 820 chipset is the first Intel chipset that supports the enhanced features of AGP 2.0. The 4X operation of the AGP interface provides for “quad-pumping” of the AGP AD (Address/ Data) and SBA (Side-band Addressing) buses.

  • Page 58: Agp Interface Signal Groups

    Set #3 — SBA[7:0] — SB_STB — SB_STB# (used in 4X mode ONLY) • Miscellaneous, Async — USB+ — USB- — OVRCNT# — PME# — TYPDET# — PERR# — SERR# — INTA# — INTB# ® 2-32 Intel 820 Chipset Design Guide...

  • Page 59: Timing Domain Routing Guidelines

    (e.g., AD[15:0] and C/BE[2:0]#), can be 4.8” to 5.8” long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2” long, and the data signals which are associated to those strobe signals (e.g., SBA[7:0]), can be 3.7” to 4.7” long. ® Intel 820 Chipset Design Guide 2-33...

  • Page 60: Agp 2x/4x Routing Example For Interfaces < 6"

    (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5 mil traces with at least 20 mils of space (1:4) between them. ® 2-34 Intel 820 Chipset Design Guide...

  • Page 61: Agp 2.0 Routing Summary

    Domain Set#3 SB_STB# length NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils 2. These guidelines apply to board stackups with 10% impedance tolerance ® Intel 820 Chipset Design Guide 2-35...

  • Page 62: Agp Clock Routing

    0.9 ns of clock skew (the motherboard designer shall ® determine how the 0.9 ns is allocated between the board and the synthesizer). For Intel chipset platform AGP clock routing guidelines, refer to Chapter 4, “Clocking”.

  • Page 63: Vddq Generation And Typedet

    AGP signals be reference to ground depending on board layout. An ideal design would have the complete AGP interface signal field referenced to ground. The recommendations above are not specific to any particular PCB stackup, but are applied to all ® Intel Chipset designs. 2.7.7 VDDQ Generation and TYPEDET# AGP specifies two separate power planes (VCC and VDDQ).

  • Page 64: Typdet#/vddq Relationship

    When this happens, the regulator drives to gate of the FET to nearly 12V. This turns the FET on and passes 3.3V - 2A * to VDDQ. DS-ON ® 2-38 Intel 820 Chipset Design Guide...

  • Page 65: Vref Generation For Agp 2.0 (2x And 4x)

    AGP interface as is practical to get the benefit of the common mode power supply effects. However, the trace spacing around the V signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity. ® Intel 820 Chipset Design Guide 2-39...

  • Page 66: Agp 2.0 Vref Generation & Distribution

    (for 3.3V add-in cards) and the source generated V (for 1.5V add-in cards). Usage of the source generated V at the receiver is optional and is a product implementation issue which is beyond the scope of this document. ® 2-40 Intel 820 Chipset Design Guide...

  • Page 67: Compensation

    0.1 inch to avoid signal reflections from the stub. The pull-up/pull-down resistor value requirements are shown in the table below: Rmin Rmax 4 KΩ 16 KΩ The recommended AGP pull-up/pull-down resistor value is 8.2 KΩ. ® Intel 820 Chipset Design Guide 2-41...

  • Page 68: Motherboard / Add-in Card Interoperability

    • Universal AGP connector. ® To maximize add-in flexibility, implementing the universal connector in Intel 820 chipset based system is strongly recommended. All add-in cards are either 3.3V or 1.5V cards. Due to timings, 4X transfers at 3.3V are not allowed.

  • Page 69: Hub Interface

    Each signal must be routed such that it meets the guidelines documented for the signal group to which it belongs. Figure 2-33. Hub Interface Signal Routing Example 1.8V 10 KΩ HL_STB HL11 HL_STB# HL[10:0] CLK66 GCLK Clocks ® Intel 820 Chipset Design Guide 2-43...

  • Page 70: Data Signals

    HREF pin. Figure 2-34. Single Hub Interface Reference Divider Circuit 1.8V 300Ω HUBREF HUBREF 0.01uF 0.01uF 300Ω 0.1uF HubRef1.vsd ® 2-44 Intel 820 Chipset Design Guide...

  • Page 71: Locally Generated Hub Interface Reference Dividers

    The MCH also has a hub interface compensation pin. This signal (HLCOMP) can be routed using either the RCOMP method or ZCOMP method described for the ICH. ® Intel 820 Chipset Design Guide 2-45...

  • Page 72: System Bus Design

    2-36. Segment lengths are defined at the pins of the devices or ® components. For 2-way processor / Intel 820 chipset designs, a termination card must be placed in the unused slot when only one processor is populated. This is necessary to ensure signal integrity requirements are met.

  • Page 73: System Bus Ground Plane Reference

    2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM) Intel is enabling a new S.E.P.P. (Single Edge Processor Package) style retention mechanism which will provide a grounding path for the heatsink on processors in the S.E.C.C. 2 package. This solution is referred to as the S.E.C.C.2 (Single Edge Contact Cartidge 2) Grounding Retention Mechanism (GRM).

  • Page 74: Hole Locations And Keepout Zones For Support Components

    The required thickness of the pad is less than 0.001” (using 1/2 oz. copper). ® 2-48 Intel 820 Chipset Design Guide...

  • Page 75: Processor Cmos Pullup Values

    ® ® ® III processor with the Intel Table 2-13 contains the pullup values for the Intel Pentium chipset. This table supports both single and dual processor configurations. Table 2-13. Processor and 82820 MCH Connection Checklist CPU Pin UP Pin Connection (CPU0)

  • Page 76

    1 KΩ pull up to Vcc2.5, 47 Ω series resistor ITP. to ITP pin 7 Tank circuit is optional for signal integrity. ~680 Ω pull down, connect to ITP pin 12 TRST# Connect to 2 processor ® 2-50 Intel 820 Chipset Design Guide...

  • Page 77

    2. This checklist supports Intel Pentium II processors at all current speeds, Intel Pentium III processors to ® ® a FMB guideline of 19.3A, and future Intel Pentium III processors to the current FMB guideline of 18.4A. ® Intel 820 Chipset Design Guide 2-51...

  • Page 78: Additional Host Bus Guidelines

    56 pF SC242 Connector B non-inverting buffer 100 nH motherboard trace 56 pF itp vsd ® Table 2-14. Bus Request Connection Scheme for DP Intel 820 Chipset Designs Bus Signal Agent 0 Pins Agent 1 Pins BREQ0# BR0# BR1# BREQ1#...

  • Page 79: Dual-processor Breq Strapping Requirements

    RESET# (RSTIN# signal from MCH). The value of the strapping needs to be held for a minimum of 2 host clocks after the deassertion of RSTIN#. Refer to the latest version of the processor datasheets for complete description on the timing requirement. ® Intel 820 Chipset Design Guide 2-53...

  • Page 80: Ha7# Strapping Option Example Circuit (for Debug Purposes Only)

    Appendix A, “Reference Design Schematics: Uni-Processor” Appendix B, “Reference Design Schematics: Dual-Processor” (e.g., HINIT#, IGNNE#, SMI#, etc.) preclude use of the Intel Pentium III processor LAI. The Intel Pentium III processor LAI will function correctly with these 1 KΩ pull-up resistors. ® 2-54...

  • Page 81

    This can create a large undershoot, followed by ringback which may violate the ringback specifications. This “wired-OR” situation should be simulated for the following signals: AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#. ® Intel 820 Chipset Design Guide 2-55...

  • Page 82: Ultra Ata/66

    80-conductor cable (e.g., Ultra ATA/33 Mode). ® After determining the Ultra DMA mode to be used, the BIOS will configure the Intel 820 chipset hardware and software to match the selected mode.

  • Page 83: Ultra Ata/66 Cable Detection

    Layout/Routing Guidelines 2.13.2 Ultra ATA/66 Cable Detection ® The Intel 820 chipset can use two methods to detect the cable type. Each mode requires a different motherboard layout. Host-Side Detection (BIOS Detects Cable Type Using GPIOs) Host side detection requires the use of two GPI pins (1 per IDE controller). The proper way to...

  • Page 84: Drive-side Ide Cable Detection

    — R2 is a 15 KΩ resistor — C1 is not stuffed • For Drive-Side Detection: — R1 is not stuffed — R2 is not stuffed — C1 is a 0.047 uF capacitor ® 2-58 Intel 820 Chipset Design Guide...

  • Page 85: Layout For Host- Or Drive-side Ide Cable Detection

    Layout/Routing Guidelines Figure 2-48. Layout for Host- or Drive-Side IDE Cable Detection Figure 2-49. Ultra ATA/66 Cable IDE Connector Black wires are ground Grey wires are signals ® Intel 820 Chipset Design Guide 2-59...

  • Page 86: Ultra Ata/66 Pullup/pulldown Requirements

    22 - 47 ohm Reset# PCIRST_BUF#* PDD[15:8] PDD[7] PDD[6:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ 5.6k 8.2k-10k PIORDY IRQ14 PDDACK# 470 ohm CSEL Pin 32 N.C. Pin 34 N.C. *Due to ringing, PCIRST# must be buffered. ® 2-60 Intel 820 Chipset Design Guide...

  • Page 87: Ac'97

    The ICH implements an AC’97 2.1 compliant digital controller. Any codec attached to the ICH AC-link must be AC’97 2.1 compliant as well. Contact your codec IHV for information on 2.1 compliant products. The AC’97 2.1 specification is on the Intel website. The ICH supports the following combinations of codecs: Table 2-15.

  • Page 88: Tee Topology Ac'97 Trace Length Requirements

    5 mil space between the traces. Figure 2-52. Tee Topology AC'97 Trace Length Requirements 4" Max Codec 2" Max 3" Max Figure 2-53. Daisy-Chain Topology AC'97 Trace Length Requirements Codec 3" Max 5" Max ® 2-62 Intel 820 Chipset Design Guide...

  • Page 89: Ac'97 Signal Quality Requirements

    (ICH), and any other codec present. That clock is used as the timebase for latching and driving data. ® On the Intel 820 chipset platform, the ICH supports Wake on Ring from S1, S3, and S4 via the AC’97 link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem codec.

  • Page 90

    The ICH0/ICH provides internal weak pulldowns. Therefore, the motherboard does not need to provide discrete pulldown resistors. • PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction of a pop when powering the mixer up or down. ® 2-64 Intel 820 Chipset Design Guide...

  • Page 91: Usb

    Figure 2-54. USB Data Signals Motherboard Trace Driver 15 ohm < 1" 45 ohm 47 pf 90 ohm Motherboard Trace Driver 15 ohm < 1" 45 ohm 47 pf Transmission Line USB Twisted Pair Cable ® Intel 820 Chipset Design Guide 2-65...

  • Page 92: Isa (82380ab)

    — PICCLK must be connected from the clock generator to the PICCLK pin on the processor — Connect PICD0 to 2.5V through 10 KΩ resistors — Connect PICD1 to 2.5V through 10 KΩ resistors ® 2-66 Intel 820 Chipset Design Guide...

  • Page 93: Smbus/alert Bus

    RAM when the system is powered down. This section will present the recommended hookup for the RTC circuit for the ICH. This circuit is not the same as the circuit used for the PIIX4. ® Intel 820 Chipset Design Guide 2-67...

  • Page 94: Rtc Crystal

    (C2 and C3): Equation 2-4. External Capacitance Calculation Cload = (C2 * C3)/(C2+C3) + Cparasitic C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain the 32.768 kHz. ® 2-68 Intel 820 Chipset Design Guide...

  • Page 95: Rtc Layout Considerations

    A standby power supply should be used in a desktop system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby increase the RTC accuracy. ® Intel 820 Chipset Design Guide 2-69...

  • Page 96: Rtc External Rtcrst Circuit

    • Put a ground plane under all of the external RTC circuitry • Do not route any switching signals under the external components (unless on the other side of the ground plane) ® 2-70 Intel 820 Chipset Design Guide...

  • Page 97: Vbias Dc Voltage And Noise Measurements

    Excess noise on VBIAS can cause the ICH internal oscillator to misbehave or even stop completely. • To minimize noise of VBIAS, it is necessary to implement the routing guidelines described above and the required external RTC circuitry. ® Intel 820 Chipset Design Guide 2-71...

  • Page 98

    Layout/Routing Guidelines This page is intentionally left blank. ® 2-72 Intel 820 Chipset Design Guide...

  • Page 99: Advanced System Bus Design

    Advanced System Bus Design...

  • Page 100

    This page is intentionally left blank.

  • Page 101: Terminology And Definitions

    Section 3.2, “AGTL+ Design Guidelines” on page 3-4 discusses specific system guidelines. This is a step-by-step methodology that Intel has successfully used to design high performance desktop systems. Section 3.3, “Theory” on page 3-15 introduces the theories that are applicable to this layout guideline.

  • Page 102

    It is an enhancement to the GTL (Gunning Transceiver Logic) technology. See thePentium® II Processor Developer’s Manual for more details of GTL+. ® Intel 820 Chipset Design Guide...

  • Page 103

    SSO effects. Stub The branch from the trunk terminating at the pad of an agent. Intel uses a 50 Ω test load for specifying its components. Test Load Trunk The main connection, excluding interconnect branches, terminating at agent pads.

  • Page 104: Agtl+ Design Guidelines

    AGTL+ Design Guidelines The following step-by-step guideline was developed for systems based on two processor loads and one Intel 82820 MCH load. Systems using custom chipsets will require timing analysis and analog simulations specific to those components. The guideline recommended in this section is based on experience developed at Intel while ®...

  • Page 105: Initial Timing Analysis

    Equation 3-3. Maximum Flight Time ≤ Clock Period - T - CLK - CLK FLT_MAX CO_MAX SU_MIN SKEW JITTER Equation 3-4. Minimum Flight Time ≥ T + CLK FLT_MIN HOLD SKEW CO_MIN ® Intel 820 Chipset Design Guide...

  • Page 106: Agtl+ Parameters For Example Calculations

    Table 3-3 is an example minimum flight time calculation for a 133 MHz, 2-way Pentium III processor/Intel 820 chipset system bus. Note that assumed values for clock skew and clock jitter were used. Clock skew and clock jitter values are dependent on the clock components and distribution method chosen for a particular design and must be budgeted into the initial timing equations as appropriate for each design.

  • Page 107: Example Tflt_max Calculations For 133 Mhz Bus

    2. BCLK period = 7.50 ns @ 133.33 MHz. 3. The flight times in this column include margin to account for the following phenomena that Intel has observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and signal quality and are sometimes not accounted for in simulation.

  • Page 108: Determine General Topology, Layout, And Routing Desired

    Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis. However, simulation results at the device pins may be used later to correlate simulation performance against actual system measurements.

  • Page 109

    Positioning drivers with faster edges closer to the middle of the network typically results in more noise than positioning them towards the ends. However, Intel has shown that drivers located in all positions (given appropriate variations in the other network parameters) can generate the worst- case noise margin.

  • Page 110: Place And Route Board

    ) may be 60 Ω ±15%. Intel recommends the baseboard nominal effective line impedance (Z impedance to be at 60 Ω ±15% for the recommended layout guidelines to be effective. Intel also recommends running uncoupled simulations using the Z of the package stubs; and performing fully coupled simulations if increased accuracy is needed or desired.

  • Page 111: Trace Width Space Guidelines

    BERR#, BINIT#, BNR#, HIT#, and HITM#. This document addresses AGTL+ layout for both 1 and 2-way 133 MHz/100 MHz processor/ ® Intel 820 chipset systems. Power distribution and chassis requirements for cooling, connector location, memory location, etc., may constrain the system topology and component placement location;...

  • Page 112: Picd[1,0] Uni-processor Topology

    SC242 connector BCLK pin. Note that the clock route from the clock driver to the Intel 82820 MCH will require an additional trace length of approximately 4.6” to compensate for the additional propagation delay along the processor host clock path (SC242 connector plus processor cartridge trace).

  • Page 113: Post-layout Simulation

    Intel specifies signal integrity at the device pads and therefore recommends running simulations at the device pads for signal quality. However, Intel specifies core timings at the device pins, so simulation results at the device pins should be used later to correlate simulation performance against actual system measurements.

  • Page 114: Validation

    Since both timing numbers (T and T ) include propagation time from FLIGHT-SYSTEM the pad to the pin, it is necessary to subtract this time (T ) from the reported flight time to avoid ® 3-14 Intel 820 Chipset Design Guide...

  • Page 115: Theory

    , starting from the beginning of the driver transition at the pad. T must be generated using the same test load for T . Intel provides this timing value in the AGTL+ I/O buffer models. In this manner, the following valid delay equation is satisfied: Equation 3-5.

  • Page 116: Timing Requirements

    The signal propagating in each direction causes cross-talk on the victim network. ® 3-16 Intel 820 Chipset Design Guide...

  • Page 117: Aggressor And Victim Networks

    Backward cross-talk reaches a maximum (and remains constant) when the ® Intel 820 Chipset Design Guide 3-17...

  • Page 118

    13 to 19 resistors (for 14- and 20-pin components). These packages generally have too much inductance to maintain the voltage/current needed at each resistive load. Intel recommends using discrete resistors, resistor networks with separate power/ground pins for each resistor, or working with a resistor network vendor to obtain resistor networks that have acceptable characteristics.

  • Page 119: More Details And Insight

    0 67 MICROSTRIP (ns/ft) Equation 3-9. Effective Propagation Speed ∗ S EFF (ns/ft) Equation 3-10. Effective Impedance Ω Equation 3-11. Distributed Trace Capacitance (pF/ft) Equation 3-12. Distributed Trace Inductance ∗ ∗ 0 12 (nH/ft) ® Intel 820 Chipset Design Guide 3-19...

  • Page 120: Effective Impedance And Tolerance/variation

    This method has the disadvantage of reducing area that can be used to route traces. These partial planes may also ® 3-20 Intel 820 Chipset Design Guide...

  • Page 121: One Signal Layer And One Reference Plane

    Signal Layer A Ground Plane Signal Layer B 1 f l Figure 3-8. Layer Switch with Multiple Reference Planes (same type) Signal Layer A Ground Plane Layer Layer Ground Plane Signal Layer B M lt ® Intel 820 Chipset Design Guide 3-21...

  • Page 122: Layer Switch With Multiple Reference Planes

    • A signal that transitions from a stripline or microstrip through vias or pins to a component (Intel 82820 MCH, etc.) should have close proximity decoupling across all involved reference planes to ground for the device. ®...

  • Page 123: Clock Routing

    3.4.3.4 SC242 Connector Intel studies indicate that the use of thermal reliefs on the connector pin layout pattern (especially ground pins) should be minimized. Such reliefs (cartwheels or wagon-wheels) increase the net ground inductance and reduce the integrity of the ground plane to which many signals are referenced.

  • Page 124: Definitions Of Flight Time Measurements/corrections And Signal Quality

    1.3 V (1.1 V + 200 mV) for rising edge ringback • 0.69 V (0.89 V – 200 mV) for falling edge ringback ® A violation of these ringback limits requires flight time correction as documented in the Intel Pentium II Processor Developer’s Manual. ®...

  • Page 125: Flight Time Definition And Measurement

    V -∆V crossing. Figure 3-12. Rising Edge Flight Time Measurement Receiver Pin Driver Pin into Test Load + 200 mV Overdrive Regio + 100 mV ∆V Guardband ∆V - 100 mV Tflight-max Tflight-min ® Intel 820 Chipset Design Guide 3-25...

  • Page 126: Conclusion

    Intel recommends planning a layout schedule that allows time for each of the tasks outlined in this document.

  • Page 127: Clocking

    Clocking...

  • Page 128

    This page is intentionally left blank.

  • Page 129: Clock Generation

    Clocking Clocking Clock Generation ® There are two clock generator components required in an Intel 820 chipset based system. The Direct Rambus Clock Generator (DRCG) generates clock for the Direct Rambus interface while the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the ®...

  • Page 130: Intel ® 820 Chipset Platform Clock Distribution

    MCH to phase align the direct RDRAM clock with the CPU clocks. This phase alignment information is provided to the DRCG via the SYNCLKN and PCLKM pins. ® Figure 4-1. Intel 820 Chipset Platform Clock Distribution Processor Processor...

  • Page 131: Intel ® 820 Chipset Platform Clock Skews

    Clocking ® Table 4-2. Intel 820 Chipset Platform Clock Skews Skew Clock Symbols Pin-to-Pin Board Total Relationship Notes See Figure 4-1 (ps) (ps) (ps) A leads C, SC242 HCLK to SC242 HCLK (DP ONLY) -175 +175 -125 +125 -300 +300...

  • Page 132: Intel ® 820 Chipset Clock Routing Guidelines

    Clocking ® Figure 4-2 shows the Intel 820 chipset clock length routing guidelines. ® Figure 4-2. Intel 820 Chipset Clock Routing Guidelines CPUCLK to SC242 5.3" ±0" CPUCLK to MCH Note: Tie CPUCLK for the MCH to CPUCLK to the SC242 to eliminate pin-to-pin skew.

  • Page 133: Intel ® 820 Chipset Platform System Clock Cross-reference

    Clocking ® Table 4-3. Intel 820 Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name Component Pin Name PCI Slot PCI Slot PCI Slot PCI Slot PCICLK PCI Slot PCICLK-F LPC Super I/O FWH Flash BIOS GCLKIN 3V66 CLK66 AGP Connector (on-board device)

  • Page 134: Component Placement And Interconnection Layout Requirements

    2.5V near the DRCG if the 2.5V plane extends near the DRCG. However, if a 2.5V trace must be used, it should originate at the CK133 and be routed as shown. ® Intel 820 Chipset Design Guide...

  • Page 135: Mch To Drcg

    (A) = CTM/CTM# RIMM to MCH (A) = CFM/CFM# MCH to RIMM RIMM_0 RIMM_1 (B) = RIMM to RIMM for Clocks (C) = RIMM to Termination (D) = DRCG to RIMM CFM/CFM# CTM/CTM# DRCG 0.4"-0.45" Term 0"-3.50" 0"-3" 0"-6" ® Intel 820 Chipset Design Guide...

  • Page 136: Drcg To Rdram Channel

    2.6.2.1. For the line sections labeled ‘B’ (Figure 4-5) (RIMM to RIMM) the clock signals must be matched within ±2 mils to the trace length of every RSL signal. Exact length matching is preferred. ® Intel 820 Chipset Design Guide...

  • Page 137: Differential Clock Routing Diagram (section 'a', 'c', & 'd')

    0.1 uF capacitor as shown in Figure 4-8. Figure 4-8. Termination for Direct Rambus* Clocking Signals CFM/CFM# 28 Ω 2% 27 Ω 1% 0 .1 uF 28 Ω 2% 27 Ω 1% CFM# ® Intel 820 Chipset Design Guide...

  • Page 138: Drcg Impedance Matching Circuit

    DRCG to the 28 Ω The circuit shown in Figure 4-9 channel impedance. More detailed information can be found in the Direct Rambus Clock Generator Specification. ® 4-10 Intel 820 Chipset Design Guide...

  • Page 139: Drcg Layout Example

    The rule is to keep all resistor stubs within 250 mils of the CK133. If routing rules allow, Rpacks can be used if power dissipation is not exceeded for the Rpack. ® Intel 820 Chipset Design Guide 4-11...

  • Page 140: Unused Outputs

    4.8.1 DRCG Frequency Selection Table and Jitter Specification To allow additional flexibility in board design, Intel has enabled a variation of the DRCG labeled the DRCG+. The device has the same specifications, pinout and form-factor as the existing DRCG device document. There are two modifications made to the DRCG+.

  • Page 141: Drcg+ Frequency Selection Schematic

    DRCG+ Frequency Selection Schematic DRCG+ frequency selection can be accomplished using two GPIOs connected to the MULT[0:1] ® pins as shown in Figure 4-11. This allows selection of all frequencies supported by the Intel chipset. Figure 4-11. DRCG+ Frequency Selection DRCG REFCLK...

  • Page 142

    Clocking This page is intentionally left blank. ® 4-14 Intel 820 Chipset Design Guide...

  • Page 143: System Manufacturing

    System Manufacturing...

  • Page 144

    This page is intentionally left blank.

  • Page 145: In Circuit Lpc Flash Bios Programming

    5.3.1 Overview ® The Intel 820 chipset platform requires a board stackup with a 4.5 mil prepreg. This change in dimension (previously, typically 7 mil) is required because of the signaling environment used for Direct RDRAM, AGP 2.0 and hub interface. The RDRAM Channel is designed for 28 Ω and mismatched impedance will cause signal reflections which will reduce voltage and timing margins.

  • Page 146: Pcb Materials

    Calculate board geometries for the desired impedance - or use the example stackup provided • Build test boards and coupons • Measure board impedance using a TDR and follow Intel’s Impedance Test Methodology Document (found on developer.intel.com) • Measure geometries with cross-section •...

  • Page 147: Test Coupon Design Guidelines

    Choice Separate location in the panel The Intel Impedance Test Methodology Document should be used to ensure boards are within the 28Ω ±10% requirement. The Intel Controlled Impedance Design and Test Document should be used for the test coupon design and implementation. These documents can be found at: http://developer.intel.com/design/chipsets/memory/rdram.htm...

  • Page 148: Impedance Calculation Tools

    27.7 30.4 30.2 28.0 5.3.8 Testing Board Impedance The Intel Impedance Test Methodology Document should be used to ensure boards are within the 28 Ω ±10% requirement. This document can be found at: http://developer.intel.com. ® Intel 820 Chipset Design Guide...

  • Page 149: Board Impedance/stackup Summary

    2. 2116 Cloth, 1 ply 0.0045” when cured with 53% resin is the second largest volume in production today. Due to the impedance & layout requirement of traces for Direct RDRAM, ® AGP 2.0, and hub interface, this stackup is recommended for Intel 820 chipset platform design.

  • Page 150

    System Manufacturing This page is intentionally left blank. ® Intel 820 Chipset Design Guide...

  • Page 151: System Design Considerations

    System Design Considerations...

  • Page 152

    This page is intentionally left blank.

  • Page 153: Power Delivery

    For example, 3.3VSB is usually derived (on ® the motherboard) from 5VSB using a voltage regulator (on the Intel Chipset Reference Board, 3.3VSB is derived from 5V_DUAL). Dual power rail A dual power rail is derived from different rails at different times (depending on the power state of the system).

  • Page 154: Intel

    Delivery ® Figure 6-1 shows the power delivery architecture for the Intel 820 Chipset Reference Board. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices include: main memory, the ICH resume well, PCI wake devices (via 3.3V aux) and USB (USB can...

  • Page 155

    System Design Considerations ® In addition to the power planes provided by the ATX power supply, an instantly available Intel 820 chipset based system (using Suspend-to-RAM) requires 7 power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to on- ®...

  • Page 156: V And 2.5v Power Sequencing (schottky Diode)

    System Design Considerations ® The Intel 820 Chipset Reference Board is using a switching regulator from 5V Dual. It may be possible to use a linear regulator to regulate from 3.3VSB, however the thermal characteristics must be considered. Additionally, a low drop out linear regulator would be necessary. If 2.5VSBYis regulated from 3.3VSB, it is important the 3.3VSB regulator can supply enough current for all the...

  • Page 157: 64/72mbit Rdram Excessive Power Consumption

    2.5VSBY (and controlled by SLP_S3#). If using a FET switch, the resistive drop across the FET switch should be considered. ® Note: This regulator is not required in a Intel 820 chipset based system that does not support Suspend- to-RAM (STR).

  • Page 158: Use A Gpo To Reduce Drcg Frequency

    Option 2: Increase the Current Capability of the 2.5V Voltage Regulator The second implementation option requires that the 2.5V power supply be modified to maintain the maximum amount of current required by a fully populated RDRAM channel (~7.5A). ® Intel 820 Chipset Design Guide...

  • Page 159: Power Plane Splits

    System Design Considerations Power Plane Splits ® Figure 6-4 shows an EXAMPLE of the power plane splits on an Intel 820 chipset platform. Figure 6-4. Power Plane Split Example Thermal Design Power The thermal design power is the estimated maximum possible expected power generated in a component by a realistic application.

  • Page 160: Glue Chip 3 Vendors

    Glue Chip 3 (Intel 820 Chipset Glue Chip) ® To reduce the component count and BOM cost of the Intel 820 chipset platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip. The Glue Chip 3 is designed to integrate some or all of the following functions into a single device. By integrating much of the required glue logic into a single device, overall board cost can be reduced.

  • Page 161

    Reference Board Schematics: Uni-Processor...

  • Page 162

    This page is intentionally left blank.

  • Page 163: Reference Design Schematics: Uni-processor

    Reference Design Schematics: Uni-Processor Reference Design Feature Set The reference schematics feature the following core feature set: ® • Intel 820 Chipset — Memory Controller Hub (MCH) — I/O Controller Hub (ICH) — FWH Flash BIOS Interface • Support for the Pentium III (SC242) Processor —...

  • Page 164

    *T h ird -p a rty b ra n d s a n d n a m e s a re th e p ro p e rty o f th e ir re s p e c tive o w n e rs . Voltage Regulators 29,30 Pow er Connector PCI/AGP Pullups/Pulldow ns Rambus Termination Decoupling 34,35 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 Revision History DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 165

    82559 LAN ADM1021 TPS2042 Keyboard Floppy Parallel Game Conn Mouse Serial 1 Serial 2 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: BLOCK DIAGRAM 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 166

    Contact Cartridge 2 Thermal Validation" document for further details. HD#61 HD#61 RESERVED0 Place R121,R122 very close to processor. HD#62 HD#62 HD#63 HD#63 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 167

    BERR# CPURST# RESET# AERR# B118 RES0 RES1 JP16 RES2 B112 RES3 A113 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-18-1999_11:32...

  • Page 168

    JP18 O UT O UT A c tive 133M Hz ,48M Hz P LL ac t ive* 9,12 MULT1_GPIO JP11 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: CLOCK SYNTHESIZER 1.01 DRAWN BY: PROJECT: No stuff R161, JP11. PCD PLATFORM DESIGN All jumpers may not be required, but are included for test purposes.

  • Page 169

    Place R129 and R180 less than 0.5" from MCH using 10 mil trace. HD#60 TEST/GRCOMP HD#61 40.2-1% HD#61 HD#62 HD#62 HD#63 HD#63 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 170

    SB_STB SBA5 19,32 SBSTB# SBA6 SB_STB# SBA6 19,32 SBA7 SBA7 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 No stuff. For test only. DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 171

    PGNT#4 PCICLK GNT#4 PGNT#5 GPIO17/GNT#B/GNT#5 21,32 Place HUBREF circuit between MCH and ICH HUBREF voltage = 0.9V +/- 2% TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 172

    OC#1 SDD14 2.7K OC1# SDD14 SDD15 OC#0 OC0# SDD15 SPKR_STRAP AC_SDOUT_STRAP 2.7K TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN AC_SDATAOUT 1900 PRAIRIE CITY ROAD 9,13,15 LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 12-2-1999_16:22...

  • Page 173

    TBLK_LCK F W H J P 2 1 O U T L o c k e d U n lo c k e d * TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN...

  • Page 174

    SMBDATA_CORE 3,9,11,32 RAMREF 6,11 C169 C256 C243 C236 0.1UF 0.1UF 0.1UF 0.1UF TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: RIMM SOCKETS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-24-1999_13:14...

  • Page 175

    GP22/P12 SYSOPT CLKI32 CLOCKS GP24/SYSOPT SIO_14MHZ Pulldown on SYSOPT for IO address of 0x02E CLOCKI 4.7K TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SUPER I/O 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 176

    100K No stuff AUD_VREFOUT AC_XTAL_IN AFILT1_C XTAL AFILT2_C AC_XTAL_OUT FILT_L_C 24.576MHZ AGND AGND TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: AUDIO 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-18-1999_10:46...

  • Page 177

    CD Analog Input CD_L_C CD_L CD_L_J 4.7K CD_REF_J CD_REF_C CD_REF CD_R_J 4.7K CD_R_C CD_R 4.7K TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: AUDIO 1.01 DRAWN BY: PROJECT: AGND AGND AGND PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 178

    Au d io Do w n JP 2 GND[6] GND[14] AC_BITCLK AC97_MSTRCLK AC97_BITCLK 9,13 E nable* Dis able TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: AUDIO/MODEM RISER 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 179

    SMBCLK RBIAS100 RBIAS100 ALERTDATA_SBY SMBD 9,32 VREF LAN_X1 C101 LAN_X2 22PF 22PF TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: LAN CONTROLLER 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-18-1999_10:48...

  • Page 180

    1 -2 No stuff C5. 470PF D is a b le 2 -3 C5 must be rated at 1500V. No stuff C31. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 181

    LED_PU1 SN74LVC07A SN74LVC07A Onboard LED indicates the standby well is on DUAL_COLOR to prevent hot swapping memory. For debug only. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SYSTEM 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 182

    AD_STB0# AD_STB0 7,32 GAD7 GAD6 GND_J GND_T GAD5 GAD4 GAD3 GAD2 VDDQ_E VDDQ_K TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: GAD1 GAD0 AGP CONNECTOR 1.01 MCH_AGPREF VREF_GC DRAWN BY: PROJECT: VREF_CG PCD PLATFORM DESIGN 7 GAD[31:0] 1900 PRAIRIE CITY ROAD...

  • Page 183

    8,16 R119 AD17 R_AD17 C_BE#0 C_BE#0 8,16 PU1_ACK64# PU1_REQ64# PU2_ACK64# PU2_REQ64# TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 1 AND 2 1.01 8,16,21 C_BE#[3:0] DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 184

    8,16 C_BE#0 C_BE#0 R117 AD22 R_AD22 8,16 PU3_ACK64# PU3_REQ64# PU4_ACK64# PU4_REQ64# TITLE: INTEL(R) 820 CHIPSET - FCPGA REFERENCE BOARD REV: PCI CONNECTORS 3 AND 4 8,16,20 C_BE#[3:0] DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 185

    P66DETECT and S66DETECT can be connected to a GPI for BIOS cable detection. VCC3_3 VCC3_3 8.2K PCIRST# PCIRST_BUF# 6,8,10,11,12,16,19,20,21 SN74LVC07A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: IDE CONNECTORS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 186: Usb Connectors

    C245 Stuff 47PF 47PF 470PF USBAGP+ USBAGP- 15 ohm resistors and 47pf caps should be within 1" of ICH TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: USB CONNECTORS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 187

    PAR_INIT# PAR_INIT#_R ERR# RP20 PDR1 PDR1_R PDR0 PDR0_R AFD# AFD#_R STB# STB#_R TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: PARALLEL PORT 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-18-1999_11:22...

  • Page 188

    CTS1_C RTS#1 RTS1_C RI#1 RI1_C VCC12- VCC-12 COM2 is a 2x5 pin header for a cabled port. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SERIAL PORTS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 189

    MDAT_FB DIR# STEP# WDATA# WGATE# MCLK MCLK_FB TRK#0 WRTPRT# RDATA# HDSEL# DSKCHG# TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: KEYBOARD/MOUSE/FLOPPY 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-18-1999_11:23 OF 36...

  • Page 190

    47PF 470PF 47PF 0.01UF 0.01UF Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: GAME PORT 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN...

  • Page 191

    VID4 ETQP6F0R8L 5 6 7 8 LTC1753 VRM_COMP 3 2 1 JP10 VID Override Jumpers Sanyo 4SP2200M TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VRM 8.2 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 192

    VOUT SHDN# SENSE VOUT VCC2_5_ADJ VCC1_8_ADJ Place C311 at regulator. Place C108 and C333 at RIMM termination TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 193

    0.1UF C312 VCC2_5SBY_BG C299 1000PF C292 C263 VCC2_5SBY_SENSE+ VCC2_5SBY_SENSE- VCC2_5SBY_VOSENSE Do not stuff C292. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 194: Power Connector

    74LVC14A C266 No stuff. For test only Resume Reset circuitry using a 22 msec delay and Schmitt trigger logic. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: POWER CONNECTOR 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 195

    8.2K R314 SERIRQ 8,12,21 R236 SMB_ALERT 8.2K 4.7K ALERTCLK_SBY 9,16 4.7K ALERTDATA_SBY TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 9,16 4.7K PCI/AGP PULLUPS/PULLDOWNS 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 196

    C277 TERM_COL3 R273 0.1UF TERM_COL4 R272 NOTE : Use one 0.1uF cap per two RSL signals. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: RAMBUS TERMINATION 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 197

    SN74LVC07A 0.01UF SN74LVC07A SN74LVC06A 74LS132 SN74LVC07A Place VDDQ capacitors within SN74LVC06A 70 mils of outer balls of MCH. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: DECOUPLING 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 198

    10UF 0.01UF 0.1UF 10UF 10UF 0.01UF 0.01UF 0.01UF Place caps at VTT pins on Slot 1 connector. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: BULK DECOUPLING 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 199

    39 ohm to 39.2 ohm resistors. Pg 34 Deleted 3.3V decoupling for RIMM connectors. Added solder side decoup for MCH. Changed VDDQ cap values from 0.1uF to 0.01uF. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: REVISION HISTORY 1.01...

  • Page 200

    Hub Link Connector For debug only. PROBE CONNECTOR TEST_CLK66 HUBREF HL_STB HL_STB# HL10 VCC1_8 P08-050-SL-A-G TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: 1.01 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 201

    Reference Board Schematics: Dual-Processor...

  • Page 202

    This page is intentionally left blank.

  • Page 203: Reference Design Schematics: Dual-processor

    Reference Design Schematics: Dual-Processor Reference Design Feature Set The reference schematics feature the following core feature set: ® • Intel 820 Chipset — Memory Controller Hub (MCH) — I/O Controller Hub (ICH) — FWH Flash BIOS interface • Support for the two Pentium III (SC242) Processors —...

  • Page 204

    PCI Co n n e c to r s 2 2 , 2 3 Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or...

  • Page 205

    Mouse U4, U6 GD75232 Serial 1 LM4880 Serial 2 LPC47B27X ADM1021 ADM1021 TPS2042 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: BLOCK DIAGRAM 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 206

    Contact Cartridge 2 Thermal Validation" document for further details. HD#61 HD#61 RESERVED0 Place R19, R100 very close to processor. HD#62 HD#62 HD#63 HD#63 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 207

    ITP Config JP33 JP34 Single CPU0 Dual CPU Single CPU1 JP33 JP34 TDO_0 TDI_0 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 4 TDI PROCESSOR CONNECTOR 3.03 DRAWN BY: PROJECT: TDO_1 PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 208

    Contact Cartridge 2 Thermal Validation" document for further details. HD#61 HD#61 RESERVED0 Place R121, R122 very close to processor. HD#62 HD#62 HD#63 HD#63 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 209

    C110 4,6,8 AERR# B118 RES0 RES1 JP32 RES2 B112 RES3 A113 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 210

    MULT1_GPIO JP11 Active 100MHz, 48MHz PLL active Test Mode Reserved Active 133MHz,48MHz PLL inactive Active 133MHz,48MHz PLL active* TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: No stuff R161, JP11. CLOCK SYNTHESIZER 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN All jumpers may not be required, but are included for test purposes.

  • Page 211

    Place R129 and R180 less than 0.5" from MCH using 10 mil trace. HD#60 TEST/GRCOMP HD#61 40.2-1% HD#61 HD#62 HD#62 HD#63 HD#63 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 212

    SB_STB SBA5 21,34 SBSTB# SBA6 SB_STB# SBA6 21,34 SBA7 SBA7 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 No stuff. For test only. DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 213

    PCICLK GNT#4 PGNT#5 GPIO17/GNT#B/GNT#5 23,34 Place HUBREF circuit between MCH and ICH HUBREF voltage = 0.9V +/- 2% TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 214

    SDD14 OC1# SDD14 2.7K SDD15 OC#0 OC0# SDD15 SPKR_STRAP AC_SDOUT_STRAP 2.7K TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD AC_SDATAOUT LAST REVISED: SHEET: 11,15,17 FOLSOM, CALIFORNIA 95630...

  • Page 215

    R308 WPROT 4.7K JP21 Top Block Lock TBLK_LCK FW H JP21 Locked Unlocked* TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 216

    3,5,11,13,34 RAMREF 8,13 C169 C256 C243 C236 0.1UF 0.1UF 0.1UF 0.1UF TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: RIMM SOCKETS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 217

    SYSOPT CLKI32 CLOCKS GP24/SYSOPT SIO_14MHZ Pulldown on SYSOPT for IO address of 0x02E CLOCKI 4.7K TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SUPER I/O 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 218

    No stuff AUD_VREFOUT AC_XTAL_IN AFILT1_C XTAL AFILT2_C AC_XTAL_OUT FILT_L_C 24.576MHZ AGND AGND TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 219

    CD_L CD_L_J 4.7K CD_REF_J CD_REF_C CD_REF CD_R_J 4.7K R167 CD_R_C CD_R 4.7K TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO 3.03 DRAWN BY: PROJECT: AGND AGND AGND PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 220

    AC97_SDATA_IN2 AC97_SDATA_IN0 11,15 GND[6] GND[14] Enable* AC_BITCLK AC97_MSTRCLK AC97_BITCLK 11,15 Disable TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO/MODEM RISER 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 221

    RBIAS100 RBIAS100 ALERTDATA_SBY SMBD 11,34 VREF LAN_X1 C101 LAN_X2 22PF 22PF TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: LAN CONTROLLER 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 222

    82559 LAN Enable* No stuff C5. 470PF C5 must be rated at 1500V. Disable No stuff C31. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 223

    LED_PU1 SN74LVC07A SN74LVC07A Onboard LED indicates the standby well is on DUAL_COLOR to prevent hot swapping memory. For debug only. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SYSTEM 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 224

    AD_STB0# AD_STB0 9,34 GAD7 GAD6 GND_J GND_T GAD5 GAD4 GAD3 GAD2 VDDQ_E VDDQ_K TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: GAD1 GAD0 AGP CONNECTOR 3.03 MCH_AGPREF VREF_GC DRAWN BY: PROJECT: VREF_CG PCD PLATFORM DESIGN 9 GAD[31:0] 1900 PRAIRIE CITY ROAD...

  • Page 225

    R119 AD17 R_AD17 C_BE#0 C_BE#0 10,18,22,23 PU1_ACK64# PU1_REQ64# PU2_ACK64# PU2_REQ64# TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 1 AND 2 3.03 10,18,23 C_BE#[3:0] DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 226

    C_BE#0 C_BE#0 R117 AD22 R_AD22 10,18,22,23 PU3_ACK64# PU3_REQ64# PU4_ACK64# PU4_REQ64# TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 3 AND 4 3.03 10,18,22 C_BE#[3:0] DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 227

    P66DETECT and S66DETECT can be connected to a GPI for BIOS cable detection. VCC3_3 VCC3_3 8.2K PCIRST# PCIRST_BUF# 8,10,12,13,14,18,21,22,23 SN74LVC07A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: IDE CONNECTORS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 228

    Stuff 47PF 47PF 470PF USBAGP+ USBAGP- 15 ohm resistors and 47pf caps should be within 1" of ICH TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: USB CONNECTORS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 229

    PAR_INIT#_R ERR# RP20 PDR1 PDR1_R PDR0 PDR0_R AFD# AFD#_R STB# STB#_R TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PARALLEL PORT 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 230

    CTS1_C RTS#1 RTS1_C RI#1 RI1_C VCC12- VCC-12 COM2 is a 2x5 pin header for a cabled port. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SERIAL PORTS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 231

    DIR# STEP# WDATA# WGATE# MCLK MCLK_FB TRK#0 WRTPRT# RDATA# HDSEL# DSKCHG# TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: KEYBOARD/MOUSE/FLOPPY 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630 11-29-1999_14:46...

  • Page 232

    47PF 470PF 47PF 0.01UF 0.01UF Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: GAME PORT 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN...

  • Page 233

    V_OUT4 GND9 Default JP16, JP27-JP30 OUT. GND4 V_OUT10 Remove RP24, R104 for VID override. V_OUT5 GND10 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET:...

  • Page 234

    VOUT SHDN# SENSE VOUT VCC2_5_ADJ VCC1_8_ADJ Place C311 at regulator. Place C108, C333 at RIMMs TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 235

    C292 VCC2_5SBY_SENSE+ VCC2_5SBY_SENSE- VCMOS Generator For Rambus VCC2_5SBY_VOSENSE VCC2_5SBY Do not stuff C292. VCMOS1_8SBY C263 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 236

    Resume Reset circuitry C335 C328 using a 22 msec delay and Schmitt trigger logic. 0.01UF 10UF JP12 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: POWER CONNECTOR 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD...

  • Page 237

    8.2K R327 A20GATE ALERTCLK_SBY 10,14 11,18 8.2K R314 4.7K SERIRQ ALERTDATA_SBY 10,14,23 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: 11,18 8.2K 4.7K PCI/AGP PULLUPS/PULLDOWNS 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 238

    TERM_COL3 R273 0.1UF TERM_COL4 R272 NOTE : Use one 0.1uF cap per two RSL signals. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: RAMBUS TERMINATION 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 239

    SN74LVC07A SN74LVC07A Place VDDQ capacitors within 70 mils of outer balls of MCH. SN74LVC06A 74LS132 SN74LVC07A SN74LVC06A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: DECOUPLING 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED:...

  • Page 240

    10UF 0.1UF 10UF 10UF 10UF 10UF 0.1UF 10UF 10UF 10UF 10UF TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: BULK DECOUPLING 3.03 DRAWN BY: PROJECT: PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD LAST REVISED: SHEET: FOLSOM, CALIFORNIA 95630...

  • Page 241

    39 ohm to 39.2 ohm resistors. Pg 36 Deleted 3.3V decoupling for RIMM connectors. Added solder side decoup for MCH. Changed VDDQ cap values from 0.1uF to 0.01uF. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: REVISION HISTORY 3.03...

  • Page 242

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