Intel 82496 CACHE CONTROLLER User Manual page 317

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS# The 82496 Cache Controller never asserts CADS# and SNPADS# on the same
ClK. There are always one or more ClKs between CADS# and a following
SNPADS#.
CDrS# CDTS# is always asserted a minimum of 1 ClK after SNPADS#.
CNA#
CNA# is ignored during snoop write back cycles (initiated with SNPADS#).
CRDY# Cycles initiated by SNPADS# require CRDY# but do not require other cycle
progress signals (BGT#, KWEND#, SWEND#).
Snoop Address and SNPADS# indicates the start of the write-back cycle. Here, the 82496 Cache
Cycle Specification
Controller drives the following address and cycle specification signals with
Signals
SNPADS#: APIC#, CCACHE#,
CD/C#,
CM/IO#, CPCD, CPWT, CSCYC,
CW/R#,
CWAY, MAP, MBE#, MCACHE#, MCFA, MSET, MTAG, NENE#, PAllC#,
RDYSRC, and SMlN#.
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