Wrarr - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.147.
WRARR#
WRARR#
Write to 82491 Cache SRAM Array
Controls the writing of data into the 82491 Cache SRAM array and updating MRU
bit.
Output from 82496 Cache Controller (pin M15), Input to 82491 Cache SRAM (pin
44)
Synchronous to ClK
Signal Description
WRARR#, when active, latches the WAY signal in the 82491 Cache SRAM to decide which
way should be updated or what MRU value to write.
For read cycles which miss the MRU bit, the 82491 Cache SRAM will update the MRU bit 1
CLK after WRARR# is sampled active. The WAY signal value becomes the MRU value.
For write cycles, WRARR# qualifies the WAY input to the 82491 Cache SRAM to determine
in which way the data will be written.
Relation to Other Signals
Pin Symbol Relation to Other Signals
WAY
For write cycles, WRARR# qualifies the WAY input to the 82491 Cache SRAM to
determine in which way the data will be written.
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