Intel 82496 CACHE CONTROLLER User Manual page 363

MEMORY BUS FUNCTIONAL DESCRIPTION
6.4. SNOOP HIT TO [M] STATE - SYNCHRONOUS SNOOP MODE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
ClK
ADS#
~r-','----','----''----'----'----'-----'------'----'----'----'--,
CPU_A:::
~!
! A! ! !
~
!INOB! !
! ! I! !
! !
~ ! A! ! !
CPU~::;: I I I
!
I I I I I I I'T! !~! I I I !
:~~~~I I I I I I I I I I I I I III I IY;I I I I I
:~:~:
iT
j j
jl
j j j j j jl [ [ [ [ [ [ [I [ [I j j j
SNPADS#
CWJR#
RDYSRC
MCACHE#
I I I
'--tJ
I
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~w!ss\b
!
!
~~I I
I I
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\ I I
,
\
' I
I I I I
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~,
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I I
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I I I I I ITT
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r
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SNPCYC#
MTHIT#
~I
MHITM#
'\SS\\\ 'S'\
I
SNPBSY#
SNPSTB#
MADE#
i [ i i
, ,
, ( " "
I I In,-
SNPINVtSNPNCA
NOTE:
MCLK
MSEL#
-'-'-'-'~------'_'_'~_'_'~_'-----J------'------'-----J_,_,_~,_J
::~:: s'~\ \fSS~S~'~\\ '~'\~
S\!'
\~SS\f\\y' \t\\2sstS\2S'S~ \S!\\~~\S2SS
' t SS!S\"t )
M:~~::;t;:;I.J;1
I I I I I I I I I I I I I
I~
MEDC#
-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-:~
STRtBED~DDf:
I I I I I I I I I I I I I I I
LH· -- ,l
MOSTB - -
~
- - - ,. - -
~
- - - ,. - -
~
- - - ,. - - , - - .,. - - , - - -, - - - , - - -, - - -
~
- - -, - - - ;- - - -, - - - ;- - - ., - - -
I , - - - ' , ' - - - - ' , ' - -
CDB62
1. In strobed mode, MOSTB is used in place of MBRDY to indicate data transfer off of the memory
bus.
Figure 6-9. Snoop Hit to [M] State - Synchronous Snoop Mode
Figure 6-9 illustrates a snoop hit to [M] state sequence. This example assumes synchronous
snooping mode, i.e. requests for snoop are done via SNPSTB# signal which is sampled by the
82496 Cache Controller's clock (not SNPCLK).
In clock 1, SNPSTB# is activated indicating the 82496 Cache Controller has a request for
. 6-18
I