Aperr - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.8. APERR#
APERR# Address Parity Error
Indicates that a CPU Bus address parity error occurred.
Output from 82496 Cache Controller (pin S01)
Synchronous to ClK
Glitch Free
Signal Description
APERR# is driven active in CPU cycles whenever there is a CPU address parity checking
error.
When Driven
APERR# is activated at least two CLKs after ADS#, and stays active for a minimum of one
CPU CLK. The 82496 Cache Controller begins checking address parity on the clock of the
CPU ADS#, and will keep checking until the address is internally latched. This internal
latching is guaranteed to happen before NA# or the first BRDY#.
APERR# is inactive during RESET, and remains inactive until at least 5 CLKs after RESET
goes inactive.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CFA,SET,TAG APERR# is driven active only after a wrong line address parity is driven to the
82496 Cache Controller on the AP input during a CPU cycle.
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