Intel 82496 CACHE CONTROLLER User Manual page 357

MEMORY BUS FUNCTIONAL DESCRIPTION
6.2.2. Write Miss with No Allocation or Write Hit to
[S] State Cycles
CPU_DATA
BlAST#
BRDVC#
BlEC#
CADS#
CPWT
RDVSRC
MCACHE#
PALlC#
BGTII
CNA#
KWEND#
MKEN#
SWEND#
MWBIWT#
CRDV#
MEOC#
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NOTE:
I~I
COBS9
1. In strobed mode, MOSTB is used in place of MBRDY to indicate data transfer off of the memory
bus.
Figure 6-6. Write Miss with No Allocation or Write Hit to [S] State Cycles
Figure 6-6 illustrates a sequence of pipelined posted write-through cycles. Cycles A and B
exemplify memory writes that miss the 82496 Cache Controller directory, while C and D
exemplify write hit to [S] state cycles in the 82496 Cache Controller tagram.
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