Intel 82496 CACHE CONTROLLER User Manual page 168

HARDWARE INTERFACE
5.2.2.6.
AP
AP
Address Parity
Indicates CPU address bus parity.
Input/Output between 82496 Cache Controller (pin A08), and Pentium processor
(pin P03)
Synchronous to ClK
Signal Description
AP is a CPU bus address parity signal. It indicates the parity of the Pentium processor line
address bits (i.e., A[31 :5]).
When Driven
AP is driven by the Pentium processor when AHOLD is inactive (CPU initiated cycles), and is
driven by the 82496 Cache Controller when AHOLD is active (for example, during processor
snoop, flush, or sync cycles). For processor initiated cycles, AP is valid from ADS# to NA or
BRDY#. For processor snoop cycles, the 82496 Cache Controller drives AP valid during the
CLK of EADS#. Note that BT[3:0] must be low for the 82496 Cache Controller to generate a
correct AP signal.
Relation to Other Signals
Pin Symbol Relation to Other Signals
A[31 :5] AP represents th·e parity of the Pentium processor line address, A[31 ;5], and the
corresponding 82496 Cache Controller address lines (i.e., CFA, TAG, SET).
AHOlD AP is an input to the 82496 Cache Controller (from the Pentium processor) when
AHOlD=O, and an output from the 82496 Cache Controller (to the Pentium
processor) when AHOlD= 1 .
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