Intel 82496 CACHE CONTROLLER User Manual page 182

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol
Relation to Other Signals
BGT#
BROY# must be asserted on the same ClK or after BGT# is asserted.
For Read-Miss cycles, the first BROY# must be > 1 + 4*lR ClKs from the last
SNPCYC# before BGT#. (Note: lR=Line Ratio).
BROY#(N-1)
For Read-Miss cycles, the first BROY# of cycle N must be > 4*lR ClKs from the
first BROY# of cycle N-1. (Note: lR=Line Ratio).
COTS# BROY# must be asserted after COTS# is asserted.
CROY# On CPU read cycles, the last BROY# (lBROY#) of Cycle N must be activated
prior to the CROY# of cycle N+ 1 .
KWENO# BROY# of a non-cacheable 82496 Cache Controller cycles (MKEN# returned
inactive) which is cacheable by the Pentium processor (active CACHE#), must be
issued after KWENO# (at which time KEN# is valid).
MEOC# MEOC# for cycle N+ 1 must be asserted at least one ClK after the last BROY# of
cycle N.
SNPCYC#
For Read-Miss cycles, the first BROY# must be > 1 + 4*lR ClKs from the last
SNPCYC# before BGT#. (Note: lR=Line Ratio).
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