Intel 82496 CACHE CONTROLLER User Manual page 240

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol Relation to Other Signals
CACHE# KEN# is driven inactive during cycles in which the 82496 Cache Controller
samples CACHE# inactive.
D/C#
KEN# is driven inactive during data (D/C#=1) read cycles with MRO# sampled
active.
BRDYC# KEN# is valid with either NA# or the first BRDY# of the cycle (whichever comes
first).
LOCK# KEN# is always driven inactive during locked cycles.
MKEN# If MKEN# is sampled inactive by the 82496 Cache Controller, the KEN# will be
driven inactive to the CPU.
MRO# KEN# is driven inactive during data read cycles with MRO# sampled active.
NA# KEN# is valid with either NA# or the first BRDY# of the cycle (whichever comes
first)
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