Page 1 6300ESB ICH Embedded Platform ® ® ® ® For use with the Intel Pentium M Processor, Intel Pentium ® Processor on 90 nm process with 2 MB L2 cache, and the Intel ® Celeron M Processor Design Guide October 2005 300669-006...
Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Page 3: Table Of Contents
Length Matching Constraints ................. 55 4.1.4.1 Package Length Compensation ............. 56 4.1.4.2 Trace Length Equalization Procedures ..........56 4.1.5 Asynchronous Signals ................... 58 4.1.5.1 Topology 1A: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor – IERR# ..........59...
Page 4 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 4.1.5.2 Topology 1B: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor – FERR# and THERMTRIP# .... 59 4.1.5.3 Topology 1C: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor –...
Page 5 4.4.5 GMCH Core Voltage Plane and Decoupling............101 Power and Sleep State Definitions ...................101 Power Delivery Map......................103 Intel 855GME Chipset Platform Power-Up Sequence ............105 4.7.1 GMCH Power Sequencing Requirements ............105 4.7.2 6300ESB Power Sequencing Requirements ............105 4.7.2.1...
Page 6 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 5.4.3.3 Clock Length Package Table ............... 130 5.4.4 Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0] ..........130 5.4.4.1 Data Bus Topology ................131 5.4.4.2 SDQS to Clock Length Matching Requirements........133 5.4.4.3...
Page 7 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 6.4.1 DVOB and DVOC Module Design ...............168 6.4.1.1 Generic Connector Model ..............169 DVO GMBUS and DDC Interface Considerations ............170 6.5.1 Leaving the GMCH DVOB or DVOC Port Unconnected........171 Miscellaneous Input Signals and Voltage Reference ............
Page 8 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide IDE Interface........................194 9.2.1 Cabling......................... 194 Cable Detection for Ultra ATA/66 and Ultra ATA/100............195 9.3.1 Combination Host-Side/Device-Side Cable Detection......... 195 9.3.2 Device-Side Cable Detection................196 9.3.3 Primary IDE Connector Requirements ..............
Page 9 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 9.10.1 66 MHz Topologies and Trace Length..............229 9.10.1.1 PCI-X Clock Length Matching Guidelines ..........231 9.10.2 IDSEL Series Resistor ..................231 9.10.3 PCI-X Secondary Bus Reset ................232 9.10.3.1 Secondary Bus Reset Not Utilized ............
Page 10 Layout Checklist........................299 13.1 Processor Checklist ......................299 ® 13.2 Intel 855GME Chipset GMCH (82855GME) Layout Checklist ........307 ® 13.3 Intel 6300ESB Layout Checklist ..................312 13.3.1 8-Bit Hub Interface Layout Checklist ..............312 13.3.2 Serial ATA Interface Layout Checklist ..............313 13.3.3 IDE Interface Layout Checklist ................
Page 11 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 13.3.5 AC’97 Layout Checklist..................315 13.3.5.1 RTC Layout Checklist ................315 13.3.6 PCI-X Layout Checklist ..................316 13.3.7 PCI Layout Checklist ................... 316 13.3.8 FWH Decoupling Layout Checklist ..............316...
Page 12 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Figures Embedded Intel® 855GME Chipset System Block Diagram ............26 Recommended Board Stack-up Dimensions................34 Trace Spacing versus Trace to Reference Plane Example ............38 Two-to-One Trace Spacing-to-Trace Width Example..............38 Three-to-One Trace Spacing-to-Trace Width Example ..............
Page 13 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 39 ITP_CLK to CPU ITP Interposer Layout Example ..............85 ® ® ® 40 Intel Pentium M/Celeron M Processor 1.8-V VCCA[3:0] Recommended Power Delivery and Decoupling....................87 ®...
Page 14 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 84 DPMS Circuit ..........................182 85 8-Bit Hub Interface Routing Example ..................183 86 8-Bit Hub Interface Single HIREF/HI_VSWING Generation Circuit Option A......185 87 8-Bit Hub Interface Local HIREF/HI_VSWING Generation Circuit Option B ......186 88 8-Bit Hub Interface Single HIREF/HI_VSWING Generation Circuit Option C ......
Page 15 148 Routing Illustration for INIT# (for Intel Pentium M/Celeron M Processor) ......267 ® ® ® 149 Voltage Translation Circuit for PROCHOT# (for Intel Pentium M/Celeron M Processor)... 268 150 Reference Voltage Level for SMVREF ..................274 ® 151 Intel 855GME Chipset HXSWING and HYSWING Reference Voltage Generation Circuit......................
Page 16 25 Analog Supply Filter Requirements ..................117 26 Power Signal Decoupling ......................121 ® 27 Intel 855GME Chipset DDR Signal Groups................123 28 Length Matching Formulas ....................... 124 29 Clock Signal Mapping ....................... 125 30 DDR Clock Signal Group Routing Guidelines ................126 31 DDR Clock Package Lengths ....................
Page 17 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 42 CPC Group Package Lengths ....................150 43 Recommended GMCH DAC Components ................156 44 Signal Group and Signal Pair Names ..................158 45 LVDS Signal Trace Length Matching Requirements ..............159 46 LVDS Signal Group Routing Guidelines ...................160...
Page 18 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 92 PCI 33 MHz Clock Signals Routing Summary................226 93 IOAPIC Interrupt Inputs 16 through 23 Usage................227 94 PCI-X Slot/Device Configurations..................... 228 95 PCI-X Routing Summary ......................228 96 PCI-X Frequencies ........................
Page 19 147 Power Checklist ........................297 148 Processor Layout Checklist ......................300 ® 149 Intel 855GME Chipset GMCH Layout Checklist ..............307 150 8-Bit Hub Interface Layout Checklist ..................312 151 Serial ATA Interface Layout Checklist ..................313 152 IDE Interface Layout Checklist ....................314 153 USB 2.0 Layout Checklist ......................
Page 20 -Updated all lntel 6300ESB information in chapter 9 to match the DG insert rev 1.6: Layout and routing, FWH, GPIO and Power managment. -Updated table 104 with 855GME spec update change (package lengths) from November 2004 revision. ® -Updated Chapter 12 with all lntel 6300ESB recommendations to match DG insert rev 1.6.
Page 21: Introduction
Note: Unless otherwise noted, all design considerations for the Intel Pentium M Processor may also be used for the Intel Pentium M Processor on 90 nm process with 2 MB L2 cache, or the Intel Celeron ®...
Page 22 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction Table 1. Conventions and Terminology (Sheet 2 of 2) Convention/ Definition Terminology Hub Interface High Speed – Refers to USB 2.0 High Speed Integrated Device Electronics...
Page 23: Reference Documents
Intel 855GM Chipset Graphics and Memory Controller Hub (GMCH) Specification Update chipsets/specupdt/253572.htm ® http://developer.intel.com/design/ Intel 855GME Chipset Graphics and Memory Controller Hub (GMCH) Specification Update Addendum for Embedded Applications intarch/specupdt/274004.htm ® ® Intel 855GME and Intel 852GM Chipset Memory Controller Hub http://developer.intel.com/design/...
Page 24 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 25: System Overview
855GME chipset contains a Graphics Memory Controller Hub (GMCH) component for embedded platforms. The GMCH provides the processor interface, system memory interface ® (DDR SDRAM), hub interface, CRT, LVDS, and a DVO interface. It is optimized for the Intel ® ®...
Page 26: Embedded Intel® 855Gme Chipset System Block Diagram
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Overview Figure 1. Embedded Intel® 855GME Chipset System Block Diagram Pentium® M Voltage Processor Regulator 400 MHz Pentium® M Processor DVO B/C Intel® 855GME Interface (GMCH)
Page 27: Component Features
M Processor on 90 nm Process with 2 MB L2 Cache All features of the Intel Pentium M processor are supported by the Intel Pentium M Processor on the 90 nm process with 2 MB L2 cache. The processors also utilize the same package and footprint.
Page 28: Intel ® Celeron ® M Processor
Celeron M Processor on 90 nm process Most features of the Intel Pentium M processor on 90 nm process with 2 MB L2 cache are ® supported by the Intel Celeron M processor on 90nm process. For more details, see the Intel ®...
Page 29: Intel ® 855Gme Chipset Graphics Memory Controller Hub (82855Gme)
— On-die 512-KB L2 Cache — TDP = 7 W — VCC-CORE: 1.004 V — V : 1.8 V supported — 479-ball micro FCBGA package ® 2.3.6 Intel 855GME Chipset Graphics Memory Controller Hub (82855GME) ® ® ® ® 2.3.6.1 Intel Pentium...
Page 30 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Overview — Zone Rendering — High quality performance Texture Engine • Analog Display Support — 350-MHz integrated 24-bit RAMDAC — Hardware color cursor support — Accompanying I2C and DDC channels provided through multiplexed interface —...
Page 31: Packaging/Power
AC’97 2.2 interface • PCI-X 1.0 interface at 66MHz • PCI 2.2 interface • Two Serial I/O ports • Two-Stage Watchdog timer 2.3.8 Firmware Hub (FWH) • An integrated hardware Random Number Generator (RNG) on Intel parts • Register-based locking January 2007...
Page 32: Packaging/Power
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Overview • Hardware-based locking • Five GPIs 2.3.8.1 Packaging/Power • 32-pin TSOP/PLCC • 3.3-V core and 3.3 V/12 V for fast programming...
Page 33: General Design Considerations
When the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design. Even when the guidelines are followed, Intel recommends that critical signals be simulated to ensure proper signal integrity and flight time. Any deviation from the guidelines shall be simulated.
Page 34: Recommended Board Stack-Up Dimensions
Intel Pentium M/Celeron M Processor FSB or DDR system memory are routed. In the remaining sections of the motherboard layout the Layer 4 and Layer 5 layers are used for power delivery.
Page 35: Alternate Stack-Ups
GND stitching vias that would stitch all the GND plane layers in that area of the motherboard. Due to the arrangement of the Intel Pentium M/Celeron M Processor and Intel 855GME chipset Graphics Memory Controller Hub (82855GME) pin-maps, GND vias placed near all GND lands are also very close to high-speed signals that may be transitioning to an internal layer.
Page 36 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide General Design Considerations...
Page 37: Intel ® Pentium ® M/Celeron ® M Processor Fsb Design And Power Delivery Guidelines
M Processor FSB Design Recommendations For proper operation of the Intel Pentium M/Celeron M Processor and the Intel 855GME chipset, it is necessary that the system designer meet the timing and voltage specification of each component. The following recommendations are Intel’s best guidelines based on extensive simulation and experimentation that make assumptions, which may be different from an OEM’s system design.
Page 38: Trace Space To Trace Width Ratio
M Processor FSB Design and Power Delivery Guidelines effects of crosstalk are difficult to simulate. The timing and layout guidelines for the Intel Pentium M/Celeron M Processor have been created with the assumption of a 2:1 trace spacing to reference plane ratio.
Page 39: Signal Propagation Time-To-Distance Relationship And Assumptions
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines relationship given below does not take into account the normal tolerances that are allowed for in the recommended board stack-up’s parameters.
Page 40: Common Clock Signals
Although every attempt shall be made to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath the GMCH and the Intel Pentium M/Celeron M Processor package outlines and up to 200–300 mils outside the package outline.
Page 41: Package Length Compensation
ADS# = 997 mils board trace + 454 Intel Pentium M/Celeron M Processor PKG + 761 GMCH PKG = 2212 pad-to-pad length. BR0# = X mils board trace + 465 Intel Pentium M/Celeron M Processor PKG + 336 GMCH PKG = 2212 pad-to-pad length.
Page 42: Source Synchronous Signals General Routing Guidelines
All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination resistors connected in a point-to-point, Zo = 55 Ω controlled impedance topology between the Intel Pentium M/Celeron M Processor and the GMCH. No external termination is needed on these signals.
Page 43: Signals Gnd Referencing To Layer 5 And Layer 7 Ground Planes
Intel Pentium M/Celeron M Processor and Intel 855GME chipset package outlines with the vias of the ground pins of the Intel Pentium M/Celeron M Processor and Intel 855GME chipset pin-map.
Page 44: Data Signals
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Figure 9. Layer 6 Intel Pentium M/Celeron M Processor FSB Source Synchronous...
Page 45: Source Synchronous Address Signals
Intel Pentium M/Celeron M Processor FSB source synchronous DATA and ADDRESS signals may reference ground planes on both Layer 2 and Layer 4. In the socket cavity of the Intel Pentium M/Celeron M Processor, Layer 3 is used for VCC core power delivery to reduce the I*R drop.
Page 46: Signals Gnd Referencing To Layer 2 And Layer 4 Ground Planes
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Figure 11. Layer 3 Intel Pentium M/Celeron M Processor FSB Source Synchronous...
Page 47: Source Synchronous - Data Group
12 mil spacing (i.e., 16 mil minimum pitch) for a 4 mil trace width. Practical cases of escape routing under the GMCH or Intel Pentium M/Celeron M Processor package outline and vicinity may not even allow the implementation of 2:1 trace spacing requirements. Although every attempt...
Page 48: Source Synchronous - Address Group
2. All length matching formulas are based on GMCH die-pad to Intel Pentium M/Celeron M Processor pin total length per byte lane. Package length tables are provided for all signals to facilitate this pad-to-pin matching.
Page 49: Intel ® Pentium ® M/Celeron ® M Processor And Intel ® 855Gme Chipset
FSB package signals within the same group are routed to the same package trace length, but the Intel 855GME chipset package signals within the same group are not routed to the same package trace length. As a result of this package length compensation is required for GMCH. Refer Section 4.1.4...
Page 50: Fsb Signal Package Lengths
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Table 9. Intel Pentium M/Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths (Sheet 1 of 6) ®...
Page 51 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Table 9. Intel Pentium M/Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths (Sheet 2 of 6) ®...
Page 52 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Table 9. Intel Pentium M/Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths (Sheet 3 of 6) ®...
Page 53 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Table 9. Intel Pentium M/Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths (Sheet 4 of 6) ®...
Page 54 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Table 9. Intel Pentium M/Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths (Sheet 5 of 6) ®...
Page 55: Length Matching Constraints
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines ® ® ® Table 9. Intel Pentium M/Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths (Sheet 6 of 6) ®...
Page 56: Package Length Compensation
4.1.4.1 Package Length Compensation The Intel Pentium M/Celeron M Processor package length does not need to be accounted for in the motherboard routing since the Intel Pentium M/Celeron M Processor has the source synchronous signals and the strobes length matched within the group inside the package routing. However trace...
Page 57: Trace Length Equalization Procedures With Allegro
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines Figure 14. Reference Trace Length Selection A29# A[31:17]# Reference Length 5950 mil 5. Use the Allegro* I (info) command to report the current length of the trace to be equalized.
Page 58: Asynchronous Signals
VCCP, the reliability and power consumption of the processor may be affected. Therefore, it is very important to follow the recommended pull-up voltage for these ® signals. All signals must meet the AC and DC specifications as documented in the Intel Pentium ® M Processor Datasheet, Intel Pentium M Processor on the 90nm Process with 2MB L2 Cache ®...
Page 59: Topology 1A: Open Drain (Od) Signals Driven By The Intel Pentium M/Celeron M Processor - Ierr
IERR# signal of the Intel Pentium M/Celeron M processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace impedance. Series resistor R1 is a dampening resistor for reducing overshoot/undershoot reflections on the transmission line.
Page 60: Topology 1C: Open Drain (Od) Signals Driven By The Intel Pentium M/Celeron M Processor - Prochot
PROCHOT# signal of the Intel Pentium M/Celeron M processor. The routing guidelines allow the signal to be routed as either a micro-strip or strip-line using 55 Ω ± 15 percent characteristic trace impedance.
Page 61: Topology 2A: Open Drain (Od) Signals Driven By And Gate-Pwrgood
PWRGOOD signal of the Intel Pentium M/Celeron M processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using 55 Ω ± 15 percent characteristic trace impedance. The pull-up voltage for termination resistor Rtt is VCCP (1.05 V).
Page 62: Topology 2B: Cmos Signals Driven By 6300Esb-Lint0/Intr, Lint1/Nmi, A20M#, Ignne#, Slp#, Smi#, And Stpclk
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK# The Topology 2B CMOS LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK# signals shall implement a point-to-point connection between the 6300ESB and the Intel Pentium M/Celeron M processor. The routing guidelines allow both signals to be routed as either micro-strip or strip-lines using 55 Ω...
Page 63: Voltage Translation Logic
Figure 22 shall be used without exception. With the low 1.05 V signaling level of the Intel Pentium M/Celeron M processor system bus, the voltage translation circuit provides ample isolation of any transients or signal reflections at the input of transistor Q1 from reaching the output of transistor Q2. Based on simulation results, the voltage translation circuit may effectively isolate transients as large as 200 mV and that last as long as 60 ns.
Page 64: Pentium ® M/Celeron ® M Processor Reset# Signal
The RESET# signal is a common clock signal driven by the GMCH CPURESET# pin. In a production system where no ITP700FLEX debug port is implemented, a simple point-to-point connection between the CPURESET# pin of the GMCH and the Intel Pentium M/Celeron M processor’s RESET# pin is recommended (see Figure 23).
Page 65: Processor Reset# Routing Example
CPURST# pin of GMCH forks out into two branches on Layer 6 of the motherboard. One branch is routed directly to the Intel Pentium M/Celeron M processor RESET# pin among the rest of the common clock signals. Another branch routes below the address signals and vias down to the secondary side that route to the Rs and Rtt resistors.
Page 66: Pentium ® M/Celeron ® M Processor And Intel 855Gme
Intel Pentium M/Celeron M processor and GMCH’s BCLK[1:0] signals, a similar transition from Layer 3 to the secondary side layer is done next to the Intel 855GME chipset package outline. Routing of the GMCH’s BCLK[1:0] signals on the secondary side is also trace tuned to 507 mils.
Page 67: Routing Recommendations
M Processor GTLREF Layout and Routing Recommendations There is one AGTL+ reference voltage pin on the Intel Pentium M/Celeron M processor, GTLREF, which is used to set the reference voltage level for the AGTL+ signals (GTLREF). The reference voltage must be supplied to the GTLREF pin. The voltage level that needs to be supplied to GTLREF must be equal to 2/3 * VCCP ±...
Page 68 GTLREF pin. The node between R1 and R2 (GTLREF) shall be connected to the GTLREF pin of the Intel Pentium M/Celeron M processor with Zo = 55 Ω trace shorter than 0.5 inches. Space any other switching signals away from GTLREF with a minimum separation of 25 mils.
Page 69: Agtl+ I/O Buffer Compensation
For the Intel Pentium M/Celeron M processor, the COMP[2] and COMP[0] pins (see Figure each must be pulled-down to ground with 27.4 Ω ± 1% resistors and shall be connected to the Intel Pentium M/Celeron M processor with a Zo = 27.4 Ω trace that is less than 0.5 inches from the processor pins.
Page 70: Resistive Compensation
Figure 33. The 18-mil wide dog bones and traces are used to achieve the Zo = 27.4 Ω target to ensure proper operation of the Intel Pentium M/Celeron M processor FSB. Refer to Figure 29...
Page 71: Primary Side Layout
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Figure 31. Intel Pentium M/Celeron M Processor COMP[3:0] Resistor Layout GTLREF[3] GTLREF[3] GTLREF[3] COMP[2] COMP[2] COMP[2] COMP[3] COMP[3] COMP[3] VCCP to VCCP to VCCP to...
Page 72: Pentium ® M/Celeron ® M Processor System Bus Strapping
The Intel Pentium M/Celeron M processor and GMCH both have pins that require termination for proper component operation. For the Intel Pentium M/Celeron M processor, a stuffing option shall be provided for the TEST[3] pin to allow a 1 kΩ ±5 percent pull-down to ground for testing purposes. For proper processor operation, the resistor shall not be stuffed.
Page 73 TEST[2:1] and RSVD (pin C16) signal resistors are placed on the secondary side of the motherboard. To avoid GND via interaction with the Intel Pentium M/Celeron M processor FSB routing, the resistors share GND via connections with the A8, A17, and A20 ground pins of the Intel Pentium M/Celeron M processor.
Page 74: Design Recommendations
1.8 V or 1.5 V power supply. For a platform supporting only Low ® ® Voltage Intel Pentium M Processors on 90 nm process with 2 MB L2 cache or Intel Celeron Processor on 90nm process, the VCCA[3:0] pin should be powered by the 1.5 V rail, since the 1.5 V rail is already required for GMCH.
Page 75: Intel System Validation Debug Support
In Target Probe (ITP). The ITP is widely used by various validation, test, and debug groups within Intel (as well as by third party BIOS vendors, OEMs, and other developers). Note: It is extremely important that any Intel Pentium M/Celeron M processor/Intel 855GME chipset- based systems designed without ITP support may prevent assistance from various Intel validation, test, and debug groups in debugging various issues.
Page 76: Pentium ® M/Celeron ® M Processor Logic Analyzer Support (Fsb Lai)
Analyzer probe. This critical tool is widely used by various validation, test, and debug groups within Intel as well as by third party BIOS vendors, OEMs, and other developers. For the Intel Pentium M/Celeron M processor, Agilent* Corporation has developed this tool and provides the only visibility to this critical system bus.
Page 77: Onboard Debug Port Routing Guidelines
Specifically, the implementation for the TDO, RESET#, and BPM[5:0]# signals on the Intel Pentium M/Celeron M processor does differ from the default ITP debug port recommendations. The changes described below should be adhered to closely.
Page 78: Itp700Flex Debug Port Signals
± 200 ps of the ITP700FLEX connector pin. 5. Route the TDO signal from the Intel Pentium M/Celeron M processor to a 54.9 Ω ± 1 percent pull-up resistor to VCCP that should be placed close to ITP700FLEX connector’s TDO pin.
Page 79 ± 50 ps., i.e., L3 + L4 – L5 = L2 (within ± 50 ps). There is no need for pull-up termination on the Intel Pentium M/Celeron M processor side of the RESET# net due to presence of AGTL+ on-die termination on the processor and the 82855GME.
Page 80: Pentium M/Celeron M Processor
Table 19. Recommended ITP700FLEX Signal Terminations (Sheet 1 of 2) Signal Termination Value Termination Voltage Termination/Decap Location Notes Within ± 300 ps of the Intel 150 Ω ± 5% VCCP (1.05 V) Pentium M/Celeron M processor CPU TDI pin Within ± 200 ps of the 39.2 Ω...
Page 81: Itp Signal Routing Example
Section 4.3.1.1 for more information. 3. All the needed terminations to ensure proper signal quality are integrated inside the Intel Pentium M/Celeron M processor AGTL+ buffers or inside the ITP700FLEX debug port. No need for any external components for the BPM[5:0]# signals.
Page 82: Itp_Clk Routing To Itp700Flex Connector
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 4.3.1.3 ITP_CLK Routing to ITP700FLEX Connector A layout example for ITP_CLK/ITP_CLK# routing to an ITP700FLEX connector is shown in Figure 37. The CK409 clock chip is mounted on the primary side of the motherboard and the differential clock pair breaks out on the same side.
Page 83: Itp700Flex Design Guidelines For Production Systems
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Figure 38. ITP700FLEX Signals Layout Example Primary Side Secondary Side 1.05 v 150 Ω VCCA=1.8 v TRST# 1.05 v 27.4 Ω 1.05 v BPM[5:0]# 680 Ω VTT, VTAP 39.2 Ω...
Page 84: Recommended Itp Interposer Debug Port Implementation
4.3.2 Recommended ITP Interposer Debug Port Implementation Intel is working with American Arium* to provide ITP interposer cards for use in debugging Intel Pentium M/Celeron M processor-based systems as an alternative to the onboard ITP700FLEX in cases where the onboard connector cannot be supported. The ITP interposer card is an additional...
Page 85: Itp Interposer Design Guidelines For Production Systems
Due to the complexity of a Intel Pentium M/Celeron M processor-based system, the LAI is critical in providing the ability to probe and capture Intel Pentium M/Celeron M processor system bus signals.
Page 86: Mechanical Considerations
VCCA[3:0] pins feed and decoupling. The 1.8 V flood on Layer 3 from the Intel 855GME chipset is a via routed up to the primary side layer with a cluster of five 1.8 V vias and two GND stitching vias as shown on the left...
Page 87: Power Delivery And Decoupling
VCCA1 decoupling capacitors are placed on the primary side on the bottom right corner of the Intel Pentium M/Celeron M processor socket. No via is required to connect the VCCA1 side of the decoupling capacitors to the VCCA1 pin. A small ground plane connects the groundside of the 1206 form factor 10 µF VCCA1 capacitors with a pair of vias to an internal ground plane.
Page 88: Processor Pll Voltage Supply Power Sequencing
(0603 MLCC, >= X7R) High-Frequency Decoupling 4 x 10 nF Place next to the Intel Pentium M/Celeron M processor CPU. NOTES: 1. VCCA[3:0] should be tied to Vcc1_8S. 2. One 10 µF and one 10 nF capacitor pair should be used for each VCCA pin.
Page 89: Thermal Power Dissipation
M Processor Power Status Indicator (PSI#) Signal PSI# is located at pin E1 of the Intel Pentium M/Celeron M processor pin-map and may be used to: • Improve the light load efficiency of the voltage regulator, resulting in platform power savings •...
Page 90: Intel ® Pentium ® M/Celeron ® M Processor Decoupling Recommendations
M Processor Decoupling Recommendations Intel recommends proper design and layout of the system board bulk and high-frequency decoupling capacitor solution to meet the transient tolerance at the processor package balls. To meet the transient response of the processor, it is necessary to properly place bulk and high-frequency capacitors close to the processor power and ground pins.
Page 91: High-Frequency/Mid-Frequency And Bulk Decoupling Capacitors
VR from any other side other than this V corridor on the north CC-CORE side of the Intel Pentium M/Celeron M processor socket. Due to the high current demand, all the and ground vias of the Intel Pentium M/Celeron M processor pin-map shall have vias CC-CORE that are connected to both internal and external power planes.
Page 92: Intel ® Pentium ® M/Celeron ® M Processor Socket Core Power Delivery Corridor
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Figure 42. Intel Pentium M/Celeron M Processor Socket Core Power Delivery Corridor VR Feed VR Feed 49 VCC/GND 49 VCC/GND Pairs Pairs 24 VCC/GND...
Page 93: Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery And Decoupling Concept Example (Option #4)
In this example, (option 4) bulk-decoupling 220 µF SP capacitors from V decoupling CC-CORE option 4 are placed on the north side of the secondary side layer in the Intel Pentium M/Celeron M processor V power delivery corridor. Notice the VRM feed point (sense resistor CC-CORE connection) is on the positive terminal side of the 220 µF SP capacitors.
Page 94 However, when comparing all four options, option 4 is the recommended V decoupling CC-CORE solution for Intel Pentium M/Celeron M processor-based systems. Option 4 offers the benefits of robust electrical performance, comparable efficiency, minimal cost, minimal motherboard surface area requirements, and lowest acoustic noise. Option 4 is a polymer-covered aluminum and ceramic-decoupling capacitor based solution that implements four polymer-covered aluminum (SP type) capacitors that have a low ESR of 12 m Ω...
Page 95 Compared to options 1-3, option 4 represents cost- and space-optimized decoupling solutions that provide a competitive level of VRM performance and efficiency. Option 4 is the recommended decoupling solution for Intel Pentium M/Celeron M processor-based systems and offers CC-CORE the best balance of performance, cost, and motherboard surface area requirements.
Page 96 GND stitching connections are shared CC-CORE with the ‘north corridor’ and ground pins of the AF signal row of the Intel Pentium M/Celeron M processor socket. To allow good current flow from the SP capacitors to the north side of the V...
Page 97 45. Two are on the side closest to the signal column 24 and 25 of the Intel Pentium M/Celeron M processor pins while one is on the side closest to signal column 2. The area between these three capacitors may be efficiently used for VRM sense resistor...
Page 98 4 compared to options 1 to 3 is the use of 0612 reverse geometry capacitors. To be effective, these 0612 capacitors need to occupy the space within the Intel Pentium M/Celeron M processor socket cavity shadow on the secondary side for both the north and south sides of the pin-map as well as outside the socket shadow along the ‘north power corridor’...
Page 99: North Corridor' Zoom-In View
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Figure 45. Intel Pentium M/Celeron M Processor Core Power Delivery ‘North Corridor’ Zoom-in View 4x220uF SP Cap 4x220uF SP Cap Primary Side Sense Resistors...
Page 100: Processor And Gmch Vccp Voltage Plane And Decoupling
The 400 MHz high-frequency operation of the Intel Pentium M/Celeron M processor and 82855GME’s Intel Pentium M/Celeron M processor FSB requires careful attention to the design of the power delivery for VCCP (1.05 V) to the Intel Pentium M/Celeron M processor and GMCH. Refer to Table 22 that presents and summarizes the VCCP voltage rail decoupling requirements.
Page 101: Gmch Core Voltage Plane And Decoupling
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® ® ® Table 22. Intel Pentium M/Celeron M Processor V Decoupling Guidelines Description Notes Low-Frequency Decoupling (Polymer-Covered 42 m Ω (typ)/2 2 x 150 µF 2.5 nH/2 Tantalum –...
Page 102 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 103: Power Delivery Map
Power Delivery Map Figure 48 depicts power delivery map for an example Intel 855GME chipset/6300ESB platform. During STR, only the necessary devices are powered. These devices include: main memory, the 6300ESB resume well, PCI wake devices (via 3.3 Vaux), AC’97, and USB. To ensure that enough power is available during STR, a thorough power budget shall be completed.
Page 104 3.3 V, 0.5A 6.0A 1 mA in S3,S5 5 V, 1.0A 5 V, 0.1A Note: Contact your Intel sales field representative for more information on the electrical requirements for ® ® DC-to-DC voltage regulator (IMVP-IV) for the Pentium M Processor/Intel Celeron...
Page 105: Intel 855Gme Chipset Platform Power-Up Sequence
855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Intel 855GME Chipset Platform Power-Up Sequence The following sections describe the power-on timing sequence for Intel 855GME chipset Graphics Memory Controller Hub (82855GME) based platforms. 4.7.1 GMCH Power Sequencing Requirements All GMCH power rails shall be stable before PWROK is asserted.
Page 106: V/1.5V Power Sequencing
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide VccSus5) will always be powered up before VccSus3_3 and thus circuitry to satisfy the sequence requirement is not needed. However, in platforms that do not derive the VccSus3_3 rail from the VccSus5 rail, this rule must be observed in the platform design as described above.
Page 107: Intel 855Gme Chipset Platform Power Delivery Guidelines
To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins. Intel recommends that the developer use the amount of decoupling capacitors specified in this document to ensure the component maintains stable supply voltages.
Page 108: Intel 855Gme Chipset And Decoupling Guidelines
® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 4.8.1 Intel 855GME Chipset and Decoupling Guidelines Decoupling in Table 24 is based on the voltage regulator solution used on the customer reference board design. Table 24. GMCH Decoupling Recommendations...
Page 109: Ddr Sdram Vdd Decoupling
GMCH are met. Refer to the following documents for the latest details on voltage and current requirements found in this design guide. • JEDEC Standard, JESD79, Double Data Rate (DDR) SDRAM Specification • JEDEC 184-Pin Unbuffered DDR DIMM Specification • Intel 855GM/855GME Chipset (GMCH) Datasheet January 2007...
Page 110: Power Delivery Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Figure 52. DDR Power Delivery Block Diagram Switching Regulator +V2_5 Vout Sense Adj. 50 - 150 Ω 50 - 150 Ω SMVREF Switching Regulator +V1_25 Vout Sense Adj.
Page 111: Gmch And Ddr Smvref Design Recommendations
DDR SMRCOMP Resistive Compensation The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer ® characteristics to specific board and operation environment characteristics. Refer to the Intel 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet and Figure 53 for details on resistive compensation.
Page 112: Ddr Vtt Termination
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Figure 54. GMCH System Memory Reference Voltage Generation Circuit +VCCSM +VCCSM 150 Ω +1% 604Ω +1% SMVSWINGH SMVSWINGL SMVSWINGL SMVSWINGH 855GME 150 Ω +1% 604 Ω +1% 0.1 μF...
Page 113: Other Gmch Reference Voltage And Analog Power Delivery
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide 4.8.3 Other GMCH Reference Voltage and Analog Power Delivery 4.8.3.1 GMCH GTLVREF For GMCH, the GTLREF generation circuit has been broken down into three separate voltage references: host data reference voltage (HDVREF[2:0]), host address reference voltage (HAVREF) and host common clock reference voltage (HCCVREF).
Page 114 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Figure 57. GMCH HCCVREF Reference Voltage Generation Circuit +VCCP 49.9 GMCH_HCCVREF HCCVREF ® Intel 855GME 0.1uF Chipset Sample layout for GMCH VREF generation is shown in Figure 58 Figure Figure 58.
Page 115: Gmch Agtl+ I/O Buffer Compensation
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Figure 59. Secondary Side of the Motherboard Layout 4.8.3.2 GMCH AGTL+ I/O Buffer Compensation The HXRCOMP and HYRCOMP pins of the GMCH shall each be pulled-down to ground with a 27.4 Ω...
Page 116: Gmch Analog Power
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide be placed within 0.5 inches of their respective pins and connected with a 15 mil wide trace. To avoid coupling with any other signals, maintain a minimum of 25 mils of separation to other signals.
Page 117 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Table 25. Analog Supply Filter Requirements Required ® Intel 855GME Rdamp Rdamp location Cbulk Chigh Chipset Filters 1210 1.0 µH VCCASM None 100 µF 0603 0.1 µF X5R DCRmax 0.169 Ω...
Page 118: Intel ® 6300Esb Power Delivery
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® 4.8.4 Intel 6300ESB Power Delivery ® Figure 63. Intel 6300ESB Power Delivery Example ATX Power Supply 5VSB 5 V 3.3 V +12 V –12 V V_REG_5V_POWER...
Page 119: Power Supply Ps_On Consideration
For 6300ESB preliminary power requirements on this rail, see Table 26. For decoupling considerations, see Section 4.8.9, “Intel® 6300ESB Decoupling Recommendations” on page 120. Note: This regulator is required in ALL designs. 3.3 VSB: The 3.3 VSB plane powers the I/O buffers in the resume well of the 6300ESB and the PCI 3.3 Vaux suspend power pins.
Page 120: Intel ® 6300Esb Analog Power Delivery
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide The ATX spec does not specify a minimum pulse width on PS_ON de-assertion; power supplies must be able to handle any pulse width. This issue may affect any power supply (beyond ATX) with similar PS_ON circuitry.
Page 121: 6300Esb Power Signal Decoupling
Thermal Design Power ® Refer to the Intel 855GME Chipset Memory Controller Hub (MCH) Thermal Design Guide for ® Embedded Applications and the Intel 6300ESB I/O Controller Hub Thermal and Mechanical Design Guide for information on thermal design.
Page 122 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 123: System Memory Design Guidelines (Ddr-Sdram)
Introduction ® The Intel 855GME Chipset Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: data, control, command, CPC, clock, and feedback signals. Table 27 summarizes the ®...
Page 124: Length Matching And Length Formulas
As mentioned above, all length matching is done for GMCH die-pad to DIMM pin. The reason for this is to compensate for the package length variation across each signal group in order. The Intel 855GME chipset Graphics Memory Controller Hub (82855GME) does not equalize package lengths internally as some previous GMCH components have;...
Page 125: Topologies And Routing Guidelines
Of course, there is some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation where required.
Page 126: Ddr Clock Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Figure 64. DDR Clock Routing Topology (SCK[5:0]/SCK[5:0]#) G M C H D IM M P A D S G M C H D iffe ren tia l P a irs NOTE: R1 is located on the DIMM module.
Page 127: Clock Length Matching Requirements
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Table 30. DDR Clock Signal Group Routing Guidelines (Sheet 2 of 2) Parameter Definition Package Length Range – P1 1000 mils ± 350 mils Refer to clock package length for exact lengths.
Page 128: Clock Reference Lengths
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) The two traces associated with each clock pair are length matched within the package, however some additional compensation may be required on the motherboard in order to achieve the ±10-mil length tolerance within the pair.
Page 129 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Figure 65. DDR Clock Trace Length Matching Diagram DIMM0 Clock Reference Length X0 = _______ GMCH Package SCK0 SCK0 Length = X0 ®...
Page 130: Clock Length Package Table
SCK/SCK# clock pair between the GMCH and the associated DIMM socket. Intel recommends that die-pad to DIMM pin length be tuned to within ± 25 mils in order to optimize timing margins on the interface.
Page 131: Data Bus Topology
The tables and diagrams below depict the recommended topology and layout routing guidelines for the DDR-SDRAM data signals. Intel recommends that the full data bus SDQ[63:0], mask bus SDM[7:0], and strobe signals SDQS[7:0] be routed on the same internal signal layer. It is required that the SDQ byte group and the associated SDM and SDQS signals within a byte lane be routed on the same internal layer.
Page 132 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Table 32 presents the data signal group routing guidelines. Table 32. Data Signal Group Routing Guidelines Parameter Definition Signal Group SDQ[71:0], SDQS[8:0], SDM[8:0]...
Page 133: Sdqs To Clock Length Matching Requirements
Length matching is only performed from the GMCH to the DIMMs, and does not involve the length of L4, which may vary over its entire range. Intel recommends that routing segment length L3 between DIMM0 to DIMM1 be held fairly constant and equal to the offset between clock reference lengths X0 and X1.
Page 134: Data To Strobe Length Matching Requirements
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Figure 67 depicts the SDQS to clock trace length matching diagram. Figure 67. SDQS to Clock Trace Length Matching Diagram DIMM0 GMCH Package...
Page 135: Sdq To Sdqs Mapping
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Length matching is not required from the DIMM1 to the parallel termination resistors. Figure 68 presents the length matching requirements between the SDQ, SDM, and SDQS signals within a byte lane.
Page 136: Sdq/Sdqs Signal Package Lengths
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Figure 68. SDQ/SDM to SDQS Trace Length Matching Diagram DIMM0 SDQ[0] GMCH Package SDQ[1] SDQ Length (Y) = (X ±25 mils) SDQ[2]...
Page 137 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Table 34. DDR SDQ/SDM/SDQS Package Lengths (Sheet 1 of 2) Pkg Length Pkg Length Signal Pin Number Signal Pin Number (mils) (mils)
Page 138: Control Signals - Scke[3:0], Scs[3:0]
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Table 34. DDR SDQ/SDM/SDQS Package Lengths (Sheet 2 of 2) Pkg Length Pkg Length Signal Pin Number Signal Pin Number (mils) (mils)
Page 139: Control Signal Routing Topology
All internal and external signals shall be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer.
Page 140: Control Signal Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) 5.4.5.2 Control Signal Routing Guidelines Table 36 defines the control signal routing guidelines. Table 36. Control Signal Routing Guidelines Parameter Routing Guidelines...
Page 141: Control Signal To Clock Trace Length Matching Diagram
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Length range formula for DIMM1: = SCK[5:3]/SCK[5:3]# total reference length, including package length. Refer to Section 5.4.3.1 for more information. = SCS[3:2]# and SCKE[3:2] total length = GMCH package length + L1, as shown in...
Page 142: Control Group Package Length Table
DIMM1. After DIMM1, transition to the same internal layer or stay on the external layer and route the signal to Rt. Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals shall be ground referenced to keep the path of the return current continuous.
Page 143: Command Topology Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Figure 71. Command Routing for Topology M C H V tt M C H P in D IM M 0 P A D...
Page 144: Command Topology Length Matching Requirements
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Table 38. Command Topology Routing Guidelines (Sheet 2 of 2) Parameter Routing Guidelines 56 Ω ± 5% Parallel Termination Resistor (Rt) Maximum Recommended Motherboard Via Count...
Page 145 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Figure 72. Topology Command Signal to Clock Trace Length Matching Diagram DIMM0 SMA[12:6,3,0] GMCH Package SBA[1:0], SRAS#, SCAS#, CMD Length = Y0 855GME (X0 –...
Page 146: Command Group Package Length Table
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) 5.4.6.4 Command Group Package Length Table The package length data in Table 39 shall be used to match the overall length of each command signal to its associated clock reference length.
Page 147: Cpc Signal Routing Topology
All internal and external signals shall be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer.
Page 148: Cpc Signal Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) 5.4.7.2 CPC Signal Routing Guidelines Table 41 presents CPC control signal routing guidelines. Table 41. CPC Control Signal Routing Guidelines Parameter Routing Guidelines...
Page 149 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Length range formula for DIMM1: = SCK[5:3]/SCK[5:3]# total reference length, including package length. Refer to Section 5.4.1 for more information. = SMAB[5,4,2,1] total length = GMCH Package length + L1, as shown in...
Page 150: Cpc Group Package Length Table
The 82855GME provides a feedback signal called ‘receive enable’ (RCVENIN#), which is used to measure timing for memory read data. The Intel 855GME chipset has the RCVENOUT# signal shunted directly to RCVENIN# inside the package to reduce timing variation. With this change it is no longer necessary to provide an external connection.
Page 151: Dram Clock Flexibility
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) Note: All three differential clocks per DDR DIMM must be routed and driven to each respective DIMM connector, regardless of ECC support.
Page 152 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines (DDR-SDRAM)
Page 153: Integrated Graphics Display Port
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port Integrated Graphics Display Port The GMCH contains four display ports: an analog CRT port, a dedicated LVDS port, and two 12-bit Digital Video Out (DVO) ports.
Page 154: Ramdac Board Design Guidelines
(R#, G#, and B#) shall be grounded to the ground plane. Intel recommends that the pi filter and terminating resistors be placed as close as possible to the VGA connector. After the 75 Ω termination resistor, the RGB signals shall continue on to their pi filters and the VGA connector, but shall now ideally be routed with a 75 Ω...
Page 155: Dac Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port 6.1.4 DAC Routing Guidelines Figure 75 presents the GMCH DAC routing guidelines. Figure 75. GMCH DAC Routing Guidelines 1.5 V Place C1 and C2...
Page 156: Rset Placement
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port The DAC channel (red, green, blue) outputs are routed as single-ended shielded current output routes that are terminated prior to connecting to the video PI-filter and VGA connector.
Page 157: Dac Power Requirements
— ± 0.95 percent from 10 MHz to maximum pixel clock frequency • Absolute minimum voltage at the VCCA package ball = 1.40 V ® Refer to the latest Intel 855GM/855GME Chipset (GMCH) Datasheet for latest AC/DC specification. January 2007...
Page 158: Hsync And Vsync Design Considerations
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port 6.1.6 HSYNC and VSYNC Design Considerations HSYNC and VSYNC signals are connected to the analog display attached to the VGA connector. These are 3.3 V outputs from the GMCH. A 39 Ω series resistor is required before routing to the VGA connector.
Page 159: Length Matching Constraints
Of course, there is some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation.
Page 160: Lvds Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port 6.2.2 LVDS Routing Guidelines Table 46. LVDS Signal Group Routing Guidelines Parameter Definition Signal Group LVDS Topology Differential Pair Point to Point Reference Plane Ground Referenced 100 Ω...
Page 161: Digital Video Out Port
(e.g., TV encoder, TMDS transmitter or integrated TV encoder and TMDS transmitter). The 82855GME has two dedicated Digital Video Out Ports (DVOB and DVOC). Intel’s DVO port is a 1.5 V only interface that may support transactions up to 165 MHz. Some of the DVO port command signals may require voltage translation circuit depending on the third party device.
Page 162: Dvo Interface Signal Groups
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port 6.3.1 DVO Interface Signal Groups Table 48 shows the DVO interface signal groups. Table 48. DVO Interface Signal Groups Signal GMCH Signal Signal...
Page 163: Dvob And Dvoc Port Interface Routing Guidelines
DPMS GPIPE# 6.3.2 DVOB and DVOC Port Interface Routing Guidelines For Intel 855GME chipset platforms, guidelines apply for both interfaces. 6.3.2.1 Length Mismatch Requirements The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
Page 164: Package Length Compensation
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package...
Page 165: Dvob And Dvoc Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port 6.3.2.3 DVOB and DVOC Routing Guidelines Table 51 provides the DVOB and DVOC routing guideline summary. Table 51. DVOB and DVOC Routing Guideline Summary...
Page 166: Dvob And Dvoc Port Termination
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port Table 52. DVOB Interface Package Lengths (Sheet 2 of 2) Signal Pin Number Package Length (mils) DVOBD[1] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7]...
Page 167: Dvob And Dvoc Assumptions, Definitions, And Specifications
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port 6.3.3 DVOB and DVOC Assumptions, Definitions, and Specifications The source synchronous solution space consists of all designs in which the flight time mismatch...
Page 168: Dvob And Dvoc Port Flexible (Modular) Design
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port Figure 79. Driver-Receiver Waveforms Relationship Specification Driver Strobe Driver Data1 Data2 Data3 Data4 Data tDVb tDVa Clock Delay Data Delay Receiver Strobe Receiver...
Page 169: Generic Connector Model
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port Figure 80. DVO Enabled Simulation Model DVOB & Connector DVOC I/F with tDVb, tDVa tDVb, tDVa, module tDSu, tDh tDSu, tDh GMCH Generic Connector All signals shall be routed as striplines (inner layers).All signals in a signal group shall be routed on...
Page 170: Dvo Gmbus And Ddc Interface Considerations
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port DVO GMBUS and DDC Interface Considerations The GMCH DVOB and/or DVOC port controls the video front-end devices via the GMBUS (I interface. DDCADATA and DDCACLK shall be connected to the CRT connector. The GMBUS shall be connected to the DVO device, as required by the specifications for those devices.
Page 171: Leaving The Gmch Dvob Or Dvoc Port Unconnected
40.2 Ω 1 percent resistor using a routing guideline of 10 mil trace and 20 mil spacing. ® • DPMS: Connects to 1.5 V version of the Intel 6300ESB SUSCLK or a clock that runs during • GVREF: Reference voltage for the DVOB and DVOC input buffers. Refer to Figure 82 proper signal conditioning.
Page 172 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port...
Page 173: Agp Port Design Guidelines
AGP Interface Specification, Revision 2.0, which can be found at http://www.agpforum.org. AGP Interface The 855GME AGP buffers operate in only one mode: 1.5-V drive, not 3.3-V safe. This mode is compliant with the AGP 2.0 Specification. AGP 4X, 2X and 1X must operate at 1.5 V. The AGP interface supports up to 4X AGP signaling.
Page 174: Agp Interface Signal Groups
® ® Intel 855GME Chipset and Intel 82801DB ICH4 Embedded Platform Design Guide AGP Port Design Guidelines 7.1.2 AGP Interface Signal Groups The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals. Each group has different routing requirements.
Page 175: Agp Routing Guidelines
® ® Intel 855GME Chipset and Intel 82801DB ICH4 Embedded Platform Design Guide AGP Port Design Guidelines AGP Routing Guidelines 7.2.1 1x Timing Domain Routing Guidelines 7.2.1.1 Trace Length Requirements for AGP 1X This section contains information on the 1X timing domain routing guidelines. The AGP 1X timing...
Page 176: Trace Spacing Requirements
® ® Intel 855GME Chipset and Intel 82801DB ICH4 Embedded Platform Design Guide AGP Port Design Guidelines The maximum line length and mismatch requirements are dependent on the routing rules used on the motherboard. These routing rules were created to give design freedom by making tradeoffs between signal coupling (trace spacing) and line lengths.
Page 177: Trace Length Mismatch Requirements
® ® Intel 855GME Chipset and Intel 82801DB ICH4 Embedded Platform Design Guide AGP Port Design Guidelines 7.2.2.3 Trace Length Mismatch Requirements Table 61. AGP 2.0 Data Lengths Relative to Strobe Length Max Trace Length Trace Spacing Strobe Length Min Trace Length Max Trace Length <...
Page 178: Agp Signal Noise Decoupling Guidelines
AGP Signal Noise Decoupling Guidelines The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the Intel chipset GMCH. The following guidelines are not intended to replace thorough system validation on Intel chipset-based products.
Page 179: Agp Routing Ground Reference
GAD31 GPAR 7.2.6 AGP Routing Ground Reference Intel strongly recommends that at least the following critical signals be referenced to ground from the GMCH to an AGP controller connector using a minimum number of vias on each net: • AD_STB0 •...
Page 180: Pull-Ups
Pull-Up NOTES: 1. The Intel chipset GMCH has integrated pull-ups to ensure that these signals do not float when there is no add-in card in the connector. 2. The Intel chipset GMCH does not implement the PERR# and SERR# signals. Pull-ups on the motherboard are required for AGP graphics controllers that implement these signals.
Page 181: Agp Vddq And Vcc
However, the trace spacing around the Vref signals must be a minimum of 25 mils to reduce crosstalk and maintain signal integrity. 7.2.10 AGP Compensation The 855GME chipset GMCH AGP interface supports resistive buffer compensation. For PCBs Ω Ω with characteristic impedance of 55 , tie the GRCOMP pin to a 40.2...
Page 182: Dpms Circuit
® ® Intel 855GME Chipset and Intel 82801DB ICH4 Embedded Platform Design Guide AGP Port Design Guidelines Figure 84. DPMS Circuit Q6D2 Q6D1 BSS138 BSS138 AGP_PIPE#_FET PM_SUS_CLK DPMS_CLK 7 19,37 DPMS_CLK +V12S 17,23,27,37,45 R6D7 100K AGP_TYPEDET# Design Guide...
Page 183: Hub Interface
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface Hub Interface The GMCH and 6300ESB ballout assignments have been optimized to simplify the Hub Interface routing between these devices. It is recommended that the Hub Interface signals be routed directly from the GMCH to the 6300ESB with all signals referenced to V .
Page 184: 8-Bit Hub Interface Signal Referencing
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface 8.1.2 8-Bit Hub Interface Signal Referencing The 8-bit Hub Interface data signal traces (HI[11:0]) and the two Hub Interface strobe signals (HI_STB/HI_STBS and HI_STB#/HI_STBF) must all be referenced to ground to insure proper noise immunity.
Page 185 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface Note: HIREF and HI_VSWING is derived from 1.5 V which is the nominal core voltage for the ± 6300ESB. Voltage supply tolerance for driver voltage must be within a 5% range of nominal.
Page 186 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface Figure 87. 8-Bit Hub Interface Local HIREF/HI_VSWING Generation Circuit Option B 1. Each 0.01 µF bypass capacitor should be placed within 0.25 inches of HIREF/VREF pin (C4) and HI_VSWING pin (C2).
Page 187: Gmch Single Generated Voltage Reference Divider Circuit
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface Figure 89. 8-Bit Hub Interface Local HIREF/HI_VSWING Generation Circuit Option D 1. Each 0.01 µF bypass capacitor should be placed within 0.25 inches of HIREF/VREF pin (C4) and HI_VSWING pin (C2).
Page 188: Separate Gmch Voltage Divider Circuits For Hlvref And Pswing
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface Table 69. Recommended Resistor Values for Single VREF/VSWING Divider Circuit Recommended Resistor Values VCCHI R1 = 80.6 Ω ± 1% R2 = 51.1 Ω ± 1% R3 = 40.2 Ω...
Page 189: Hub Interface Compensation
(the method of termination is dependant upon the Northbridge). This Hub Interface ® connects the Intel 855GME chipset Graphics Memory Controller Hub (82855GME) to the 6300ESB. As shown in Table 71, the 6300ESB shall strap its HLRCOMP pin to V HI = 1.5 V...
Page 190 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 191: Intel ® 6300Esb Design Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines ® Intel 6300ESB Design Guidelines Serial ATA Interface 9.1.1 Layout Guidelines Note: These routing guidelines are created using the stack-ups described in Section 3.1, “Nominal Board...
Page 192: Serial Ata Trace Length Pair Matching
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 92. Serial ATA Trace Spacing Recommendation Low-speed Differential Differential Clock/High-Speed Non-Periodic Pair Pair Periodic Signal Signal 7.0 6.0 Distance in Mils B1127-01 9.1.1.3...
Page 193: Sataled# Implementation
500 mils 9.1.1.6 SATALED# Implementation The 6300ESB provides a signal (SATALED#) to indicate SATA device activity. In order for this signal to work in conjunction with Parallel ATA hard drives, Intel recommends implementing the glue logic shown in Figure Figure 94.
Page 194: Ide Interface
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines IDE Interface Note: These routing guidelines are created using the stack-up described in Section 3.1, “Nominal Board Stack-Up” on page This section contains guidelines for connecting and routing the 6300ESB IDE interface. The 6300ESB has two independent IDE channels.
Page 195: Cable Detection For Ultra Ata/66 And Ultra Ata/100
Ultra DMA Mode 2 (Ultra ATA/33). Intel recommends that cable detection be performed using a combination Host-Side/Device-Side detection mechanism. Note that Host-Side detection cannot be implemented on an NLX form factor system, since this configuration does not define interconnect pins for the PDIAG#/CBLID# from the riser (containing the ATA connectors) to the motherboard.
Page 196: Device-Side Cable Detection
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 95. Combination Host-Side/Device-Side IDE Cable Detection To Secondary IDE Connector IDE Drive 3.3 V 3.3 V GPIO ® Intel 6300ESB I/O...
Page 197: Device Side Ide Cable Detection
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 96. Device Side IDE Cable Detection This mechanism creates a resistor-capacitor (RC) time constant. Hard drives supporting Ultra DMA modes greater than two (Ultra DMA/33) drive PDIAG#/CBLID# low and then release it (pulled up through a 10 K Ω...
Page 198: Primary Ide Connector Requirements
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.3.3 Primary IDE Connector Requirements Figure 97. Connection Requirements for Primary IDE Connector 22 Ω - 47 Ω series resistors are required on PCIRST#. The correct value should be determined •...
Page 199: Secondary Ide Connector Requirements
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.3.4 Secondary IDE Connector Requirements Figure 98. Connection Requirements for Secondary IDE Connector 22 Ω - 47 Ω series resistors are required on PCIRST#. The correct value should be determined •...
Page 200: 6300Esb Ac'97 - Codec Connection
2. The primary codec must be connected to AC_SDIN2 when also routing to CNR. If CNR does not exist on ® the platform, the primary codec may be connected to AC_8DIN0 as documented in the Intel 6300ESB I/O Controller Hub Datasheet Note: The following routing guidelines are created using the stack-up described in Section 3.1, “Nominal...
Page 201: Ac'97 Ac_Bit_Clk Routing Summary
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Using the assumed six layer stack-up, the AC’97 interface may be routed using 5 mil traces with 10 mil spacing between the traces. Maximum length between the 6300ESB and the CODEC/CNR is 14 inches.
Page 202: 6300Esb Ac'97 - Ac_Sdout/Ac_Sync Topology
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 101. 6300ESB AC'97 – AC_SDOUT/AC_SYNC Topology Table 77. AC’97 AC_SDOUT/AC_SYNC Routing Summary AC_SDOUT/AC_ Trace AC’97 Routing Series Termination Trace Lengths SYNC Signal...
Page 203: Ac'97 Routing
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Table 78. AC’97 AC_SDIN Routing Summary Trace AC’97 Routing Series Termination AC_SDIN Signal Trace Lengths Impedance Requirements Resistance Length Matching Y1 = 3 to 6 inches...
Page 204: Motherboard Implementation
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines • All resistors in the signal path or on the voltage reference should be metal film. Carbon resistors may be used for DC voltages and the power supply path, where the voltage coefficient, temperature coefficient, and noise are not factors.
Page 205: Valid Codec Configurations
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.4.2.1 Valid Codec Configurations Table 79 describes the valid codec configurations. Table 79. Supported Codec Configurations Option Primary Codec Secondary Codec Tertiary Codec...
Page 206: Ac_Sdout Pin Consideration
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.4.4 AC_SDOUT Pin Consideration AC_SDOUT is used as both the output signal to the system speaker and as a functional strap. The strap function enables or disables the Safe Mode function based on the state of the AC_SDOUT pin on the rising edge of PWROK.
Page 207: Ac'97 Audio Codec Detect Circuit And Configuration Options
AC’97 Audio Codec Detect Circuit and Configuration Options Table 80 provides general circuits to implement a number of different codec configurations. Please refer to the Communication Network Riser Specification, Revision 1.2, for Intel’s recommended codec configurations Table 80. Signal Descriptions...
Page 208: Motherboard Ac'97 Cnr Implementation With A Single Codec Down On Board
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 105. Motherboard AC’97 CNR Implementation with a Single Codec Down On Board...
Page 209: Cnr Routing Summary
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 106. Motherboard AC’97 CNR Implementation without Codec Down On Board Motherboard (CNR 1.2 Compliant) ® From Intel AC_RST# 6300ESB I/O Cntrlr...
Page 210: Usb 2.0
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines USB 2.0 9.6.1 Layout Guidelines Note: These routing guidelines are created using the stack-ups described in Section 3.1, “Nominal Board Stack-Up” on page 9.6.1.1...
Page 211: Usb 2.0 Trace Separation
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 107. Trace Routing 45” B1159-01 9.6.1.2 USB 2.0 Trace Separation Use the following separation guidelines. Figure 108 provides illustration of the recommended trace spacing.
Page 212: Usb 2.0 Termination
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 109. USB BIAS Connections Table 82. USB BIAS Routing Summary Trace USBRBIAS/USBRBIAS# Maximum Trace Signal Length Signal Impedance Routing Requirements Length...
Page 213: Plane Splits, Voids And Cut-Outs (Anti-Etch)
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines USB 2.0 CNR Trace Length Guidelines (Common-mode Choke, 55 Ω ± 10%) Table 84. Maximum Differential Maximum CNR Card Pair Spacing Motherboard Trace...
Page 214: Gnd Plane Splits, Voids, And Cut-Outs (Anti-Etch)
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines When crossing a plane split is completely unavoidable, proper placement of stitching caps may minimize the adverse effects on EMI and signal quality performance caused by crossing the split.
Page 215: Common-Mode Chokes
This technique doesn’t work for USB 2.0 due to the much higher signal rate of high-speed data. ESD protection is needed for USB lines. Refer to the Intel® ICH Family USB ESD Considerations Application Note for ESD protection implementation guidelines. A device that has been tested successfully is based on spark gap technology.
Page 216: Front Panel Solutions
The front panel internal cable solution must meet all the requirements of Chapter 6 of the Universal Serial Bus Specification, Revision 2.0 , for High-/Full-speed cabling for each port with the exceptions described in Cable Option 2. For more information refer to the Intel FPIO design guideline available at http://www.formfactors.org/developer/specs/fpio_design_guideline.pdf...
Page 217: Motherboard/Pcb Mating Connector
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Placing the capacitance near the USB connectors for cables that share power and ground conductors is required to ensure the system passes droop requirements. Cables that provide...
Page 218: Front Panel Connector Card
Figure 113 shows the major components associated with a typical front/side panel USB solution that uses a front panel connector card. For more information refer to the Intel FPIO design guideline available at: http://www.formfactors.org/developer/specs/fpio_design_guideline.pdf.
Page 219: Low Pin Count (Lpc) Interface
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 113. Motherboard Front Panel USB Support Motherboard Front Panel USB Ports B1165-01 Note: When designing front panel I/O in a system where a connector card will be used ensure that there aren’t duplicate EMI/ESD/thermistor components.
Page 220: General Routing And Placement
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines All the other signals have the same name on the 6300ESB and on the LPC Interface. Figure 114. LPC Interface Diagram PCI Bus...
Page 221: Smbus 2.0/Smlink Interface
SMLink heartbeat and event messages and send them out over the network. An external, Alert on LAN2*-enabled LAN Controller (e.g., Intel 82562EM/82562EX 10/100 Mbps Platform LAN Connect) will connect to the SMLink signals to receive heartbeat and event messages, as well as access the 6300ESB SMBus Slave Interface.
Page 222: Smbus Architecture & Design Considerations
LAN Controller Microcontroller on PCI Bus B1168-02 Note: Intel does not support access of the 6300ESB SMBus Slave Interface by the 6300ESB SMBus Host ® Controller. Refer to the Intel 6300ESB I/O Controller Hub Datasheet for full functionality descriptions of the SMLink and SMBus interface.
Page 223: High Power/Low Power Mixed Architecture
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines amount of current is the limiting agent on how small the resistor may be. The pull-up resistor may not be made so large that the bus time constant (Resistance X Capacitance) does not meet the SMBus rise and time specification.
Page 224: Pci
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Table 89. Bus Capacitance Reference Chart # of Devices/ Device Capacitance Includes Cap (pF) Trace Length 6300ESB Pin Capacitance CK409 Pin Capacitance...
Page 225: Pci Bus Layout Example
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 118. PCI Bus Layout Example ® Intel 6300ESB I/O Controller B1170-02 Note: When a CNR connector is placed on the platform, it will share a slot space with one of the PCI slots.
Page 226: Pci Data Signals Routing Summary
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Table 91. PCI Data Signals Routing Summary Trace Maximum Trace Length PCI Routing Requirements Topology Impedance L1 L2 L3 L4 2 Slots W1 = W2 = 0.5 inches,...
Page 227: Pirq Routing Example
NOTE: This figure is an example; it is up to the board designer to route these signals in the most efficient manner for their particular system. A PCI slot can be routed to share interrupts with any of the Intel 6300ESB I/O Controller Hub’s internal devices/functions, but at a higher latency cost.
Page 228: Pci-X Design Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.10 PCI-X Design Guidelines This section contains guidelines for connecting and routing the 6300ESB PCI-X interface. The 6300ESB supports up to four PCI-X devices. This section provides guidelines for PCI-X connector and motherboard design, including component and resistor placement.
Page 229: 66 Mhz Topologies And Trace Length
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.10.1 66 MHz Topologies and Trace Length Figure 122. 66 MHz PCI-X, Two Slots, Two Down Devices Configuration ® Intel 6300ESB I/O Controller...
Page 230: 66 Mhz Pci-X, Three Slot Configuration
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Note: For this configuration the recommended pull-up value for the PXPCICAP signal is 8.2 K Ω Table 98. 66 MHz PCI-X, One Down Device Routing Length Parameters...
Page 231: Pci-X Clock Length Matching Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 125. 66 MHz Clock Signal Configuration ® CONN Intel 6300ESB 0.7" I/O Controller Hub 2.5" Card PXPCLKO[0:3] Clock Input Down Clock...
Page 232: Pci-X Secondary Bus Reset
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Table 100. IDSEL to PXAD Bit Assignment Slot # PXAD Bit Device Number 9.10.3 PCI-X Secondary Bus Reset The Secondary Bus Reset (SBR) function on the 6300ESB enables the user to change the mode and frequency of the PCI-X Bus without resetting the entire system.
Page 233: Rtc
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines For more information on General Purpose Event (GPE) Register recommendations for Microsoft Windows operating systems refer to the document GPE Routing for Microsoft Windows, which can be found at http://www.microsoft.com/whdc/hwdev/tech/onnow/GPE_routing.mspx...
Page 234: Rtc Crystal
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 128. External Circuitry in the 6300ESB Without Use of Internal RTC 5 MΩ Internal RTCX1 RTCX2 External Connection 32 kHz B1181-01 9.11.1...
Page 235: External Capacitors
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Table 101. RTC Routing Summary Signal Trace RTC Routing Maximum Trace R1, R2, C1, and C2 Signal Length Impedance Requirements Length To Crystal...
Page 236: Rtc Layout Considerations
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines In certain conditions, both C values may be shifted away from the theoretical values (calculated values from the above equation) to obtain the closest oscillation frequency to 32.768 kHz.
Page 237: Diode Circuit To Connect Rtc External Battery
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Note: Refer to the 6300ESB I/O Controller Hub Datasheet for actual DC Current Characteristics. The voltage of the battery may affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases.
Page 238: Rtc External Rtcrst# Circuit
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.11.5 RTC External RTCRST# Circuit Figure 131. RTCRST# External Circuit for the 6300ESB RTC CCSUS DIODE/ BATTERY CIRCUIT 1.0 µF 20 K RTCRST# –...
Page 239: Susclk
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Note: V is also very sensitive to environmental conditions. BIAS 9.11.7 SUSCLK SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the quality of the oscillation signal on RTCX1 (largest voltage swing), the SUSCLK duty cycle may be between 30-70%.
Page 240: Fwh
6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.13 9.13.1 FWH Vendors ® The following vendors manufacture firmware hubs that conform to the Intel FWH Specification . Contact the vendor directly for information on packaging and density. http://www.sst.com/ http://www.st.coml ATMEL http://www.atmel.com 9.13.2 FWH Decoupling A 0.1...
Page 241: Fwh Vpp Design Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Figure 132. FWH/CPU UP Signal Topology Solution ® Intel Processor 6300ESB Voltage I/O Controller Translator B1187-02 NOTE: The recommended value for R1 depends on the Processor used in the system. See the Processor design guidelines for more info.
Page 242: Gpio Summary
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines In some instances, it is desirable to program the FWH during assembly with the device soldered down on the board. In order to decrease programming time it becomes necessary to apply 12 V to the V pin.
Page 243 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines Table 102. GPIO Summary (Sheet 2 of 2) GPIO Number Power Well Input-Output Tolerance If Not Used Core Output 3.3 V Core Output 3.3 V...
Page 244: Power Management
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines 9.15 Power Management 9.15.1 SYS_RESET# Usage Model The System Reset ball (SYS_RESET#) on the 6300ESB may be connected directly to the reset button on the system front panel, provided that the front panel header pulls this signal up to 3.3 V...
Page 245: Rtc Power Well Isolation Control
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines The circuit shown in Figure 136 may be implemented to control well isolation between the VccSUS3.3 and RTC power-wells in the event that RSMRST# is not being actively asserted during the discharge of the standby rail.
Page 246 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide ® Intel 6300ESB Design Guidelines...
Page 247: Miscellaneous Logic
10.1 Glue Chip 4* To reduce the component count and BOM (Bill of Materials) cost of the 6300ESB platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip. The 6300ESB Glue Chip is designed to integrate some or all of the following functions into a single device.
Page 248: Discrete Logic
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Miscellaneous Logic 10.2 Discrete Logic As an alternative solution, discrete circuitry may be implemented into a design instead of using the Glue Chip.
Page 249: Platform Clock Routing Guidelines
The system clocks are considered as a subsystem in themselves. At the center of this subsystem is the clock synthesizer/driver component. Several vendors offer suitable products, as defined in the Intel CK409 Synthesizer/Driver Specification . This device provides the set of clocks required to implement a platform-level motherboard solution.
Page 250 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines Figure 137 depicts the system clock subsystem including the clock generator, major platform components, and all the related clock interconnects. Figure 137. Clock Distribution Diagram...
Page 251: Clock Group Topologies And Routing Constraints
The clock synthesizer provides three pairs of 100 MHz differential clock outputs using a 0.7 V ® ® voltage swing. The 100 MHz differential clocks are driven to the Intel Pentium M processor, the GMCH, and the processor debug port with the topology shown in Figure 138.
Page 252: Host Clock Group Routing Constraints
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines Table 105. Host Clock Group Routing Constraints Parameter Definition Class Name HOST_CLK Class Type Individual Differential Pairs Topology Differential Source Shunt Terminated Reference Plane Ground Referenced (contiguous over length) 55 Ω...
Page 253: Host Clock Group General Routing Guidelines
Pentium M Processor Package Length BCLK1: 447 mils BCLK: 1138 mils ® Intel 855GME chipset GMCH Package Length BCLK#: 1145 mils CPU Socket Equivalent Length 157 mils 11.2.1.3 EMI Constraints Clocks are a significant contributor to EMI and should be treated with care. The following recommendations can aid in EMI reduction: •...
Page 254: Clk66 Clock Group
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.2 CLK66 Clock Group The 66 MHz clocks are series terminated and routed point-to-point on the motherboard, with dedicated buffers for each of the loads. These clocks are all length tuned to match each other and the CLK33 clocks.
Page 255: Clk33 Clock Group
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.3 CLK33 Clock Group The 33 MHz clocks are series terminated and routed point-to point on the motherboard with dedicated buffers for each of the loads. These clocks are length tuned to match the CLK66 clocks, however, they are out of phase due to an internal phase delay in the CK409.
Page 256: Pci Clock Group
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.4 PCI Clock Group The PCI clocks are series terminated and routed point-to-point as on the motherboard between the CK409 and the PCI connectors with dedicated buffers for of the three slots. These clocks are synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI daughtercard.
Page 257: Clk14 Clock Group
CLK14 clock group routing constraints. Figure 142. CLK14 Clock Group Topology L2 A C K 409 Intel® 6300E S B , Audio S IO , Intel® 6300ES B _U AR T Table 110. CLK14 Clock Group Routing Constraints Parameter Definition Class Name...
Page 258: Dotclk Clock Group
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.6 DOTCLK Clock Group The 48 MHz DOTCLK is series terminated and routed point-to-point on the motherboard. This clock operates independently and is not length-tuned to any other clock.
Page 259: Sscclk Clock Group
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.7 SSCCLK Clock Group The 48/66 MHz SSCCLK operates independently and is not length tuned to any other clock. This clock employs a spread-spectrum device in its path to reduce EMI. The overall clock path is...
Page 260: Usbclk Clock Group
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.8 USBCLK Clock Group The 48 MHz USBCLK is series terminated and routed point-to-point on the motherboard. This clock operates independently and is not length tuned to any other clock.
Page 261: Src Clock Group
11.2.9.1 SRC Clock Topology The clock synthesizer provides one set of 100-MHz differential clock outputs. The differential ® ® ® clocks are driven to the Intel Pentium M Processor and Embedded Intel 855GME Chipset with ® Intel 6300ESB I/O Controller Hub for serial-ATA as shown in Figure 137.
Page 262: Trace Spacing For Src Clocks
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines Table 114. SCR/SCR# Routing Guidelines (Sheet 2 of 2) Layout Guideline Value Illustration Notes Ω Motherboard Impedance – Differential typical Routing Length –...
Page 263: Src General Routing Guidelines
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines 11.2.9.2 SRC General Routing Guidelines • When routing the 100 MHz differential clocks, do not split up the two halves of a differential clock pair between layers.
Page 264 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines...
Page 265: Schematic Checklist Summary
855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Schematic Checklist Summary ® ® The following checklist provides design recommendations and guidance for Intel Pentium ® ® Celeron M processor systems with the Intel 855GME chipset.
Page 266 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 115. Connection Recommendations (Sheet 2 of 3) System Series Voltage √ Pin Name Notes Pull-up/Pull-down Termination Translation IERR# is a 1.05 V signal.
Page 267: Routing Illustration For Init
(Default: no stuff) the two resistors. For normal operation, leave the resistors unpopulated. GND[192:1] Connect to GND ® ® ® Figure 148. Routing Illustration for INIT# (for Intel Pentium M/Celeron M Processor) ® Intel 3.3V 6300ESB 3.3V V_IO_FWH...
Page 268: In Target Probe (Itp)
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary ® ® ® Figure 149. Voltage Translation Circuit for PROCHOT# (for Intel Pentium M/Celeron Processor) 3.3V 3.3V 330ohm +/-5% 1.3K To Receiver +/-5% 555%...
Page 269: Decoupling Recommendations
(0612 MLCC, X5R or better) NOTES: 1. Decoupling guidelines are recommendations based on Intel reference board design. The Intel Customer Reference Board uses option #4. This is the preferred recommendation for decoupling. 2. When deciding on overall decoupling solution, customers may need to take layout and PCB board design into consideration.
Page 270: Ck409 Clock Checklist
(0805 MLCC>= X5R) NOTES: 1. Decoupling guidelines are recommendations based on Intel reference board design. The Intel Customer Reference Board uses option #4. This is the preferred recommendation for decoupling. 2. When deciding on overall decoupling solution, customers may need to take layout and PCB board design into consideration.
Page 271 NC or connected to a test point. Terminate to PWRDWN# VCC3_CLK through The Intel CRB does not support S1M state. 1 K Ω resistor. This is the 14.318 MHz clock reference signal for the 6300ESB, SIO and LPC. Each 33 Ω ± 5%...
Page 272: Intel ® 855Gme Chipset Gmch (82855Gme) Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary ® 12.3 Intel 855GME Chipset GMCH (82855GME) Checklist 12.3.1 System Memory 12.3.1.1 GMCH System Memory Interface Checklist Table 121 presents the GMCH system memory interface checklist.
Page 273 Alternatively, refer to Section 5.5.1 information regarding GMCH clock routing flexibility. Signal voltage level = V_2P5_SM/2. Optionally, the Intel CRB may support a buffer to provide the necessary current Resistor divider to and reference voltage to SMVREF. V_2P5_SM consists of two...
Page 274: Ddr Dimm Interface Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Figure 150. Reference Voltage Level for SMVREF V _2P 5 _S M 50 +/ - 1% G M C H S M V R EF...
Page 275: Dimm Decoupling Recommendation Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.3.1.3 DIMM Decoupling Recommendation Checklist Table 123 presents the DIMM decoupling recommendation checklist. Table 123. DIMM Decoupling Recommendation Checklist √ Pin Name Notes Place one 0.1 µF cap close to every two pull-up resistors terminated to V_1P25_MEMVTT (VTT for †...
Page 276 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 124. FSB Checklist (Sheet 2 of 2) √ System Pin Name Notes Pull-up/Pull-down Refer to the CK409 Checklist for CPU[0], BCLK, CPU[0]#, CPU[1], Connect to CK409.
Page 277: Hub Interface Checklist
® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary ® Figure 151. Intel 855GME Chipset HXSWING and HYSWING Reference Voltage Generation Circuit +VCC P +VCC P R 1a H XSW ING H YSW ING]...
Page 278: Graphics Interfaces Checklist
1.5 K Ω 1% pull-down to LIBG IYAP[3:0]/ When any of these LVDS data pairs are unused, they IYAM[3:0] may be left as NC. The Intel CRB routes these data pairs directly to a 30-pin dual channel LVDS IYBP[3:0]/ connector. IYBM[3:0]...
Page 279 When this port is unused, it may be left as NC. For DVOBD[11:0] AGP these signals are: GAD[12:2]. Refer to Chapter 3.6.3 of the 855GME datasheet for exact assignment. When this port is unused, it may be left as NC. DVOBCLK,...
Page 280: Digital-To-Analog Converter (Dac) Checklist
Table 128. DAC Checklist System √ In Series Notes Name Pull-up/Pull-down 124-137 Ω 1% pull-down 137 Ω used on Intel CRB. REFSET to GND RED # Connect to GND. Need to connect to RED’s return path. BLUE # Connect to GND.
Page 281: Miscellaneous Signal Checklist
Needs to be translated from 3 V to 5 V. 10 K Ω 1% pull-up to VCC3 EXTTS_0 Used for SSC chip data control on Intel CRB. Leave this LCLKCTLB signal as NC if not used. Used for SSC chip data control on Intel CRB. Leave as LCLKCTLA NC if not used.
Page 282: Gmch Decoupling Recommendations Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 131. GMCH Decoupling Recommendations Checklist (Sheet 1 of 2) √ Pin Name Configuration Notes 0.1 µF Connect to Bulk decoupling is based on VR VCC[18:1] 150 µF...
Page 283: Intel ® 6300Esb Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 131. GMCH Decoupling Recommendations Checklist (Sheet 2 of 2) √ Pin Name Configuration Notes Connect to VCC_GPLL 0.1 µF V1P35_GMCH Connect to 0.1 µH (1 ohm series on CRB) from 0.1 µF...
Page 284 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 132. PCI-X Interface Checklist Checklist Items Recommendations Interface not used Reason/Impact When the signal is read as a logic high there is no effect.
Page 285: Pci Interface Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 132. PCI-X Interface Checklist Checklist Items Recommendations Interface not used Reason/Impact No extra pull-ups needed No extra pull-ups needed This signal is actively...
Page 286 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 133. PCI Interface Checklist (Sheet 2 of 3) Checklist Items Recommendations Interface not used Reason/Impact See PCI 2.2 Recommend an 8.2 K Ω...
Page 287 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 133. PCI Interface Checklist (Sheet 3 of 3) Checklist Items Recommendations Interface not used Reason/Impact In Non-APIC Mode, the PIRQx# signals may be routed to...
Page 288: Hub Interface Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.3 Hub Interface Checklist Table 134. Hub Interface Checklist Checklist Items Recommendations Reason/Impact When HI_11 is not used: Pull to V through a weak pull-down...
Page 289: Gpio Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.5 GPIO Checklist Table 136. GPIO Checklist Checklist Items Recommendations Reason/Impact GPI[0:7]: These pins are in the Core Power Well. These signals are inputs thus they need to be pulled up.
Page 290: Usb Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.6 USB Checklist Table 137. USB Checklist Checklist Items Recommendations Interface Not Used Reason/Impact Effective output driver USBP[0:3]P, May leave as no impedance of 45 Ω...
Page 291: Cpu Signals Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 138. Power Management Checklist (Sheet 2 of 2) Checklist Items Recommendations Reason/Impact Recommend an 8.2 K Ω pull-up resistor to V 3.3. Also recommend a Input to 6300ESB cannot float.
Page 292: System Management Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.9 System Management Checklist Table 140. System Management Checklist Checklist Items Recommendations Reason/Impact Requires external pull-up resistors. Typical value and power well determined by SMBus Architecture and Design Consideration section.
Page 293: Uart Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.11 UART Checklist Table 142. UART Checklist Checklist Items Recommendations Interface Not Used Reason/Impact May leave as no SIU0_CTS# No extra pull-ups needed connect...
Page 294: Ac'97 Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.12 AC’97 Checklist Table 143. AC’97 Checklist Checklist Items Recommendations Interface Not Used Reason/Impact No extra pull-down resistors required. This pin has a weak May leave as no internal 20 K Ω...
Page 295: Serial Ata Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 144. Miscellaneous Signals Checklist Checklist Items Recommendations Reason/Impact Strap function: No Reboot (See the 6300ESB EDS for more information) Has integrated pull-down. The integrated SPKR Section 9.4.3...
Page 296 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary Table 146. IDE Checklist (Sheet 2 of 2) Checklist Items Recommendations Interface Not Used Reason/Impact PDDACK#, PDIOR#, These signals have PDIOW#, integrated series resistors.
Page 297: Power Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary 12.4.16 Power Checklist Table 147. Power Checklist Checklist Items Recommendations Reason/Impact Use twelve 0.1 µF and four 0.01 µF decoupling caps Use six 0.1 µF and two 0.01 µF decoupling caps Use four 0.1 µF, one 0.01 µF, and one...
Page 298 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary...
Page 299: Layout Checklist
® Intel 855GME/6300ESB chipset. Items contained within the checklist attempt to address important connections to these devices and any critical supporting circuitry. This is not a complete list, and it does not ensure that a design will function properly. Refer to details in this document and the appended Customer Reference Board schematics for complete design recommendations.
Page 300 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 1 of 7) Checklist Items Recommendations Comments ® ® Intel Pentium M Processor Front Side Bus Interface Signals • Trace impedance = 55 Ω ± 15%.
Page 301 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 2 of 7) Checklist Items Recommendations Comments 6300ESB Interface Signals • May be routed as a test point or to any optional system receiver.
Page 302 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 3 of 7) Checklist Items Recommendations Comments IGNNE# • May be routed as strip-line or micro-strip with trace impedance = 55 Ω ± 15%.
Page 303 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 4 of 7) Checklist Items Recommendations Comments • When ITP700 Is Used : • Fork out this signal from GMCH ( do not...
Page 304 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 5 of 7) Checklist Items Recommendations Comments • When ITP700 Is Used : • Route from CPU pin to a pull-up resistor to VCCP placed near the debug connector TDO pin.
Page 305 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 6 of 7) Checklist Items Recommendations Comments • Terminate each signal to ground with 27.4 Ω ±1% resistors. • Connect each to CPU with a Zo = 27.4 Ω...
Page 306 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 148. Processor Layout Checklist (Sheet 7 of 7) Checklist Items Recommendations Comments • Recommended bulk decoupling: • (4) 220 µF SP caps - ESR 12 m Ω (max) and ESL 3.5 µH, placed near CPU north power...
Page 307: Intel ® 855Gme Chipset Gmch (82855Gme) Layout Checklist
855GME Chipset GMCH (82855GME) Layout Checklist ® Table 149 presents the Intel 855GME chipset GMCH layout checklist. ® Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 1 of 6) Checklist Items Recommendations Comments Host Interface Signals ADS# BNR# BPRI#...
Page 308: Intel ® 855Gme Chipset Gmch Layout Checklist
855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist ® Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 2 of 6) Checklist Items Recommendations Comments • See a detailed discussion on this topic in Section 5.4.4 •...
Page 309 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist ® Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 3 of 6) Checklist Items Recommendations Comments • See a detailed discussion on this topic in Section 5.4.7.
Page 310 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist ® Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 4 of 6) Checklist Items Recommendations Comments • Decouple VTT termination rail using one 0603 0.1 µF capacitor per two DDR signals.
Page 311 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist ® Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 5 of 6) Checklist Items Recommendations Comments • Place series resistor close to CK409, within 500 mils.
Page 312: Intel ® 6300Esb Layout Checklist
855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist ® Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 6 of 6) Checklist Items Recommendations Comments • Voltage divider components for each input • The HXSWING and HYSWING should be placed within 0.5 inches of their...
Page 313: Serial Ata Interface Layout Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist 13.3.2 Serial ATA Interface Layout Checklist Table 151. Serial ATA Interface Layout Checklist Layout Recommendations Comments Route SATA signals ground referenced. Route SATA signals using a minimum of vias and corners. This reduces signal reflections and impedance changes.
Page 314: Ide Interface Layout Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist 13.3.3 IDE Interface Layout Checklist Table 152. IDE Interface Layout Checklist Layout Recommendations Comments Traces need to be routed 5 mils wide and 7 mils spaces Max trace length is eight inches long.
Page 315: Ac'97 Layout Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 153. USB 2.0 Layout Checklist (Sheet 2 of 2) Layout Recommendations Comments Minimize the length of high-speed clock and periodic signal traces that run parallel to USB signal lines to minimize crosstalk. The minimum recommended spacing to clock signals is 100 mils.
Page 316: Pci-X Layout Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist Table 155. RTC Layout Checklist Layout Recommendations Comments RTC signals should be ground referenced. 13.3.6 PCI-X Layout Checklist Table 156. PCI-X Layout Checklist Layout Recommendations Comments Eight inches maximum to the first slot, then 1.5 inches to each...
Page 317: Power Delivery Checklist
® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist 13.3.9 Power Delivery Checklist Table 159. Power Delivery Checklist Layout Recommendations Comments Standby power rails (V5REF_Sus & VccSus3_3) should be Will reduce trace antennae implemented though planes.
Page 318 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
Page 319 ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematics Schematics ® The following schematics of the Intel 855GME chipset are included in this section. • Cover Page • TABLES: Block Diagram • TABLES: Reset Map •...
Page 320 ® ® Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematics • AUDIO: Aux-In, CD-In, Line-In: ATAPI Headers • AUDIO: Mic-In • AUDIO: Line-Out • AUDIO: Front Panel Audio Header • AUDIO: Transient Control • AUDIO: Analog VREG •...

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6300esb

Intel 855GME Design Manual

Introduction

System Overview

General Design Considerations

4 Intel Pentium M/Celeron M Processor FSB Design and Power Delivery Guidelines

Intel ® Pentium ® M/Celeron ® M Processor FSB Design and Power Delivery Guidelines

System Memory Design Guidelines (DDR-SDRAM)

Integrated Graphics Display Port

AGP Port Design Guidelines

Hub Interface

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Summary of Contents for Intel 855GME