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Intel 815 Design Manual

Chipset platform for use with universal socket 370
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Intel
815 Chipset Platform
For Use with Universal Socket 370
Design Guide
April 2001
Document Number:
298349-001

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Summary of Contents for Intel 815

  • Page 1 ® Intel 815 Chipset Platform For Use with Universal Socket 370 Design Guide April 2001 Document Number: 298349-001...
  • Page 2 Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    Power Sequencing on Wake Events ...41 4.3.1 4.3.2 System Bus Design Guidelines ...43 System Bus Routing Guidelines ...43 5.1.1 ® Intel 815 Chipset Platform Design Guide System Features ...17 Component Features...18 1.3.2.1 Graphics Memory Controller Hub (GMCH) ...18 ® 1.3.2.2 Intel 82801AA I/O Controller Hub (ICH) ...20...
  • Page 4 AGP Universal Retention Mechanism (RM) ...80 AGP Interface Signal Groups ...83 1X Timing Domain Routing Guidelines ...84 7.3.1.1 Flexible Motherboard Guidelines ...84 7.3.1.2 AGP-Only Motherboard Guidelines...84 2X/4X Timing Domain Routing Guidelines ...84 7.3.2.1 Flexible Motherboard Guidelines ...85 Intel ® 815 Chipset Platform Design Guide...
  • Page 5 Cable Detection for Ultra ATA/66...113 10.2.1 10.2.2 10.2.3 10.2.4 ® Intel 815 Chipset Platform Design Guide 7.3.2.2 AGP-Only Motherboard Guidelines...86 AGP Routing Guideline Considerations and Summary...87 AGP Clock Routing ...88 AGP Signal Noise Decoupling Guidelines...88 AGP Routing Ground Reference...89 1X AGP Down Option Timing Domain Routing Guidelines ...90 2X/4X AGP Down Timing Domain Routing Guidelines ...90...
  • Page 6 Clock Decoupling ...137 11.5 Clock Driver Frequency Strapping ...137 11.6 Clock Skew Assumptions ...138 ® 11.7 Intel CK-815 Power Gating On Wake Events ...139 Power Delivery...141 12.1 Thermal Design Power ...144 12.1.1 12.2 ATX Power Supply PWRGOOD Requirements...145 12.3 Power Management Signals ...146 12.3.1...
  • Page 7 Third-Party Vendor Information ...171 Appendix A: Customer Reference Board (CRB) ...173 ® Intel 815 Chipset Platform Design Guide AGP Interface 1X Mode Checklist...158 Designs That Do Not Use the AGP Port ...159 System Memory Interface Checklist...160 Hub Interface Checklist ...160 Digital Video Output Port Checklist ...160...
  • Page 8 Figure 38. System Memory Connectivity (3 DIMM) ...73 Figure 39. System Memory 3-DIMM Routing Topologies...74 ® Figure 40. Intel 815 Chipset Platform Decoupling Example ...76 ® Figure 41. Intel 815 Chipset Platform Decoupling Example ...77 Figure 42. AGP Left-Handed Retention Mechanism ...81 Figure 43.
  • Page 9 Figure 74. S0-S3-S0 Transition ...149 Figure 75. S0-S5-S0 Transition ...150 Figure 76. VDDQ Power Sequencing Circuit...152 Figure 77. Example 1.85V/3.3V Power Sequencing Circuit ...153 Figure 78. 3.3V/V5REF Sequencing Circuitry ...154 Figure 79. V5REF Circuitry...169 ® Intel 815 Chipset Platform Design Guide...
  • Page 10 Table 33. Power Sequencing Timing Definitions...151 Table 34. Recommendations For Unused AGP Port ...159 ® III Processor AGTL/AGTL+ Parameters for Example Calculations for 133 MHz Bus FLT_MAX Calculations (Frequency Independent) ...45 FLT_MIN 1, 2, 3 ...46 Intel ...45 ® 815 Chipset Platform Design Guide...

  • Page 11: Revision History

    Revision History Rev. No. Description Date -001 Initial Release. April 2001 ® Intel 815 Chipset Platform Design Guide...
  • Page 12 This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 13: Introduction

    Note: The system bus speed supported by the design is based on the capabilities of the processor, chipset, and clock driver. Note: The Intel 815 chipset for use with the universal socket 370 is not compatible with the ® ®...

  • Page 14: Terminology

    Odd Mode Crosstalk–coupling from single or multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching. Graphics and Memory Controller Hub. A component of the Intel platform for use with the Universal Socket 370 ®...
  • Page 15 Minimum voltage observed for a signal to extend below VSS at the device pad. Refers to the Intel 815 chipset using the “universal” PGA370 socket. In general, these designs support 66/100/133 MHz system bus operation, VRM 8.5 DC-DC ®...

  • Page 16: Reference Documents

    PCI Local Bus Specification, Revision 2.2 Universal Serial Bus Specification, Revision 1.0 System Overview The Intel 815 chipset for use with the Universal Socket 370 contains a Graphics Memory Controller Hub (GMCH) component and I/O Controller Hub (ICH) component for desktop platforms.

  • Page 17: System Features

    AC’97 audio and modem coder/decoders (codecs), instead of the traditional ISA devices. 1.3.1 System Features The Intel 815 chipset for use with the Universal Socket 370 platform contains two components: ® the Intel 82815 Graphics and Memory Controller Hub (GMCH) and the Intel Controller Hub (ICH).

  • Page 18: Component Features

    III processors (CPUID = 068xh) at 133 MHz system bus Pentium ® Celeron™ processors (CPUID = 068xh); 66 MHz system bus Intel SDRAM System 100/133 memory I/F MHz, 64 bit RAMDAC Monitor Digital FP / TVout video out Internal graphics comp_blk_1 ® 815 Chipset Platform Design Guide...
  • Page 19 133 MHz memory clock Supports ONLY 3.3V SDRAMs Packaging/Power 544 BGA with local memory port 1.85V ( 3% within margins of 1.795V to 1.9V) core and mixed 3.3V, 1.5V, and AGTL/AGTL+ I/O ® Intel 815 Chipset Platform Design Guide Introduction...

  • Page 20: Intel ® 82801Aa I/O Controller Hub (Ich)

    The hardware features of the firmware hub include: An integrated hardware Random Number Generator (RNG) Register-based locking Hardware-based locking 5 GPIs Packaging/Power 40-L TSOP and 32-L PLCC 3.3V core and 3.3V / 12V for fast programming ® Intel 815 Chipset Platform Design Guide...

  • Page 21: Platform Initiatives

    Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. When implemented, the Intel 815 chipset platform for use with the Universal Socket 370 can detect which processor is present in the socket and function accordingly.

  • Page 22: Manageability

    1.3.3.6 Manageability The Intel 815 chipset platform integrates several functions designed to manage the system and lower the system’s total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lock-ups, without the aid of an external microcontroller.

  • Page 23: Ac'97

    By implementing a split design, the audio codec can be on board and the modem codec can be placed on a riser. Intel is developing an AC’97 digital link connector. With a single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel where the external ports can be located.
  • Page 24 Introduction This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 25: General Design Considerations

    This document provides motherboard layout and routing guidelines for systems based on the Intel 815 chipset platform for use with the Universal Socket 370. The document does not discuss the functional aspects of any bus or the layout guidelines for an add-in device.
  • Page 26 General Design Considerations This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 27: Component Quadrant Layouts

    Component Quadrant Layouts Figure 4 illustrates the relative signal quadrant locations on the GMCH ballout. It does not represent the actual ballout. Refer to the Intel Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for the actual ballout.

  • Page 28: Figure 5. Ich 241-Ball Bga* Csp Quadrant Layout (Top View)

    Component Quadrant Layouts Figure 5 illustrates the relative signal quadrant locations on the ICH ballout. It does not represent the actual ballout. Refer to the Intel Datasheet for the actual ballout. Figure 5. ICH 241-Ball BGA* CSP Quadrant Layout (Top View) Pin 1 corner Figure 6.

  • Page 29: Universal Socket 370 Design

    Function In Name or Intel III Processor Number (CPUID=068xh) (CPUID=068xh) AF36 AK22 PICCLK Requires 2.5V ® Intel 815 Chipset Platform Design Guide Function In ® ® Future Pentium 0.13 Micron Socket 370 Processors ® and Intel Celeron™ Processor No connect...

  • Page 30: Table 2. Gmch Considerations For Universal Socket 370 Design

    Addition of circuitry to have VTTPWRGD gate PWROK from power supply to ICH. The ICH will hold the GMCH in reset until VTTPWRGD asserted plus 20 ms time delay to allow Intel CK-815 clocks to stabilize. ® 815 Chipset Platform Design Guide...

  • Page 31: Processor Design Requirements

    Use of Universal Socket 370 Design with Incompatible GMCH The universal socket 370 design is intended for use with the Intel 815 chipset platform for use with the universal socket 370. A universal socket 370 design populated with an earlier stepping of the GMCH is not compatible with future 0.13 micron socket 370 processors and, if used, will cause...

  • Page 32: Identifying The Processor At The Socket

    TUAL5# will be pulled to the 5V rail. Figure 8. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit Processor Pin AF36 VCC5 VT T 2.2 K ® Intel 815 Chipset Platform Design Guide VCC5 2.2 K TUAL5 M OSFET N TUAL5# Proc_Detect...

  • Page 33: Setting The Appropriate Processor Vtt Level

    1.25V or 1.5V to VTT for AGTL or AGTL+, respectively. Figure 9. VTT Selection Switch VCC3_3 10 F ® Intel 815 Chipset Platform Design Guide LT1587-ADJ Vout 0.1 F MO SFET N TUAL5 Universal Socket 370 Design 49.9...

  • Page 34: Vtt Processor Pin Ag1

    SMAA12 will be pulled down during reset to indicate to the GMCH that a future 0.13 micron socket 370 processor is in the socket. Refer to Figure 11. for an example implementation. TUAL5 ® Intel 815 Chipset Platform Design Guide Processor Pin AG 1 AG 1_Switch...

  • Page 35: Figure 11. Processor Identification Strap On Gmch

    Table 5 provides the logic decoding to determine which processor is installed in a PGA370 design. Table 5. Determining the Installed Processor via Hardware Mechanisms Processor CPUPRES# Pin AF36 Hi-Z ® Intel 815 Chipset Platform Design Guide 10 K TUAL5 Future 0.13 micron socket 370 processor installed. ® ® Intel Pentium III processor (CPUID=068xh) or Intel processor (CPUID=068xh) installed.

  • Page 36: Configuring Non-Vtt Processor Pins

    The diode is included so that repeated pressing of the reset or power button does not cause the NOTE: capacitor to build up enough charge to circumvent the 20 ms delay. CK-815. Furthermore, while the VTTPWRGD signal is connected to the VCC5 BAT54C...

  • Page 37: Vcmos Reference

    Figure 13. GTL_REF/VCMOS_REF Voltage Divider Network ® Intel 815 Chipset Platform Design Guide VCM OS Processor Pin AK22 0.1 F...

  • Page 38: Processor Signal Pwrgood

    See Figure 14 for an example implementation. Figure 14. Resistor Divider Network for Processor PWRGOOD PW RGOO D from ICH2 VCC2_5 PW RGOOD to Processor PW RGOOD_D ivider ® Intel 815 Chipset Platform Design Guide...

  • Page 39: Apic Clock Voltage Switching Requirements

    Figure 15. Voltage Switch For APIC Clock from Clock Synthesizer to Processor The 30 resistor represents the series resistor typically used in connecting the APIC clock to the NOTE: processor. ® Intel 815 Chipset Platform Design Guide IOAPIC MOSFET N Universal Socket 370 Design APICCLK_CPU TUAL5 API_CLK_SW...

  • Page 40: Gtlref Topology And Layout

    56 of the GMCH, and placed as close to the ADS# signal trace as possible. 63.4 GMCH pull-up to VTT. The resistor site should be located within 150 mils ® Intel 815 Chipset Platform Design Guide Processor gtlref_circuit...

  • Page 41: Power Sequencing On Wake Events

    12V supply. Thus, it is necessary to gate PWROK to the ICH from the power supply while the Intel CK-815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms.

  • Page 42: Gating Of Pwrok To Ich

    Gating of PWROK to ICH With power being gated to the Intel CK-815 by the signal VTTPWRGD12, it is important that the clocks to the ICH are stable before the power supply asserts PWROK to the ICH. As the clocking power gating circuitry relies on the 12V supply, there is no guarantee that these conditions will be met.

  • Page 43: System Bus Design Guidelines

    Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors with the Intel 815 chipset platform for use with the universal socket 370. The solution covers system bus speeds of 66/100/133 MHz for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors.

  • Page 44: Calculations

    Table 7 contains an example AGTL+ initial maximum flight time, and Table 8 contains an example minimum flight time calculation for a 133 MHz, uniprocessor system using the Pentium III processor and the Intel 815 chipset platform’s system bus. Note that assumed values were used for the clock skew and clock jitter.
  • Page 45 Processor NOTES: All times in nanoseconds The flight times in Table 7 include margin to account for the following phenomena that Intel observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect the flight time and signal quality and sometimes are not accounted for during simulation.

  • Page 46: General Topology And Layout Guidelines

    = 4.5, this should limit coupling to 3.4%. For example, intragroup AGTL+ Cross-Talk Type Intel PGA370 socket sys_bus_topo_PGA370 Max. Length (inches) 4.50 1, 2 Trace Width:Space Ratios 5:10 or 6:12 5:15 or 6:18 5:30 or 6:36 5:25 or 6:24 ® 815 Chipset Platform Design Guide...

  • Page 47: Motherboard Layout Rules For Agtl/Agtl+ Signals

    Processor Connector Breakout It is strongly recommended that AGTL/AGTL+ signals do not traverse multiple signal layers. Intel recommends breaking out all signals from the connector on the same layer. If routing is tight, break out from the connector on the opposite routing layer over a ground reference and cross over to main signal layer near the processor connector.
  • Page 48 Minimize the cross-sectional area of the traces. This can be done by means of narrower traces and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along the trace. ® Intel 815 Chipset Platform Design Guide...

  • Page 49: Motherboard Layout Rules For Non-Agtl/Agtl+ (Cmos) Signals

    SLP# SMI# STPCLK THERMTRIP# Route these signals on any layer or combination of layers. NOTE: ® Intel 815 Chipset Platform Design Guide Trace Width Spacing to Other Traces 5 mils 10 mils 5 mils 10 mils 5 mils 10 mils...

  • Page 50: Thrmdp And Thrmdn

    1 — Maximize (min. – 20 mils) 2 — Minimize 1 — Maximize (min. – 20 mils) bus_routing_thrmdp-thrmdn 3% for static conditions, and 1.5V 3% for static conditions, and 1.25V ® Intel 815 Chipset Platform Design Guide 9% for worst-case 9% for...

  • Page 51: Electrical Differences For Universal Pga370 Designs

    VCC rail at ½ nominal is 5 sec and THERMTRIP asserted to VTT rail at ½ nominal is 5 sec. System designers must ensure that the decoupling scheme used on these rails does not violate the THERMTRIP timing specifications. ® Intel 815 Chipset Platform Design Guide VCC1.8 Q2N3904 Can Use M BT3904 1.6 K...

  • Page 52: Pga370 Socket Definition Details

    System Bus Design Guidelines PGA370 Socket Definition Details The following table compares the pin names and functions of the Intel processors supported in the Intel 815 chipset platform for use with the universal socket 370. Table 12. Processor Pin Definition Comparison...
  • Page 53 GTL_REF AK36 AL13 Reserved AL21 Reserved AN11 Reserved AN15 Reserved AN21 Reserved ® Intel 815 Chipset Platform Design Guide System Bus Design Guidelines Pin Name Pin Name ® ® Intel Pentium Future 0.13 III Processor Micron (CPUID=068xh) Socket 370 Processors...
  • Page 54 Celeron processor (CPUID=068xh). Ground for future 0.13 micron socket 370 processors Additional AGTL/AGTL+ address Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). AGTL termination voltage for future 0.13 micron socket 370 processors ® 815 Chipset Platform Design Guide...
  • Page 55 (CPUID=068xh) Reserved Reserved Z36 2 VCC2.5 NOTES: 1. Refer to Chapter 4. 2. Refer to Section 13.2 ® Intel 815 Chipset Platform Design Guide System Bus Design Guidelines Pin Name Pin Name ® ® Intel Pentium Future 0.13 III Processor...

  • Page 56: Bsel[1:0] Implementation Differences

    FC-PGA2 are 3.3V tolerant for these signals, as are the clock and chipset. Intel CK-815 has been designed to support selections of 66 MHz, 100 MHz, and 133 MHz. The REF input pin has been redefined to be a frequency selection strap (BSEL1) during power-on and then becomes a 14 MHz reference clock output.

  • Page 57: Clkref Circuit Implementation

    See the appropriate processor datasheet for more details on the processor overshoot/undershoot specifications. ® Intel 815 Chipset Platform Design Guide PGA370 Vcc3.3 CLKREF 4.7 µF R2 (...

  • Page 58: Processor Reset Requirements

    Table 14. RESET#/RESET2# Routing Guidelines (see Figure 25) Parameter LenCS LenITP LenCPU cs_rtt_stub cpu_rtt_stub lenITP cs_rtt_stub lenCS lenCPU Minimum (in) Maximum (in) Intel series resistor or the Daisy chain cpu_rtt_stub Pin X4 Processor Pin AH4 10 pF sys_bus_reset_routin ® 815 Chipset Platform Design Guide...

  • Page 59: Processor Pll Filter Recommendations

    Processor PLL Filter Recommendations Intel PGA370 processors have internal phase lock loop (PLL) clock generators that are analog and require quiet power supplies to minimize jitter. 5.9.1 Topology The general desired topology for these PLLs is shown in Figure 27. Not shown are the parasitic routing and local decoupling capacitors.

  • Page 60: Figure 26. Filter Specification

    R < 2 . This also means pass-band (from DC to 1 Hz) attenuation < 0.5 dB for VCC = 1.1V, and < 0.35 dB for VCC = 1.5V. Forbidden Zone 1 MHz fpeak passband Intel Forbidden Zone 66 MHz fcore high frequency band filter_spec ® 815 Chipset Platform Design Guide...

  • Page 61: Recommendation For Intel Platforms

    5.9.3 Recommendation for Intel Platforms The following tables contain examples of components that meet Intel’s recommendations, when configured in the topology of Figure 27. Table 15. Component Recommendations – Inductor Part Number TDK MLF2012A4R7KT Murata LQG21N4R7K00T1 Murata LQG21C4R7N00 Table 16. Component Recommendations – Capacitor...

  • Page 62: Figure 27. Example Pll Filter Using A Discrete Resistor

    Figure 27. Example PLL Filter Using a Discrete Resistor CORE Discrete resistor Figure 28. Example PLL Filter Using a Buried Resistor CORE T race resistance <0.1 route PLL1 PLL2 <0.1 route <0.1 route PLL1 PLL2 <0.1 route ® Intel 815 Chipset Platform Design Guide Processor PLL_filter_1 Processor PLL_filter_2...

  • Page 63: Custom Solutions

    7. For other modules (interposer, DMM, etc.), adjust routing resistor if desired, but use minimum numbers. 5.10 Voltage Regulation Guidelines A universal PGA370 design will need the voltage regulation module (VRM) or on-board voltage regulator (VR) to be compliant with Intel VRM 8.5 DC-DC Converter Design Guidelines. 5.11 Decoupling Guidelines for Universal PGA370 Designs These preliminary decoupling guidelines for universal PGA370 designs are estimated to meet the specifications of VRM 8.5 DC-DC Converter Design Guidelines.

  • Page 64: Vtt Decoupling Design

    Twenty 0.1 F capacitors in 0603 packages placed as closed as possible to the processor VTT pins. The capacitors are shown on the exterior of the previous figure. 5.11.3 VREF Decoupling Design Four 0.1 F capacitors in 0603 package placed near VREF pins (within 500 mils). ® Intel 815 Chipset Platform Design Guide...

  • Page 65: Thermal Considerations

    Note portions of the heatsink and attach hardware hang over the motherboard. Adhering to these keepout areas will ensure compatibility with Intel boxed processor products and Intel enabled third party vendor thermal solutions for high frequency processors. While the...

  • Page 66: Figure 31. Heatsink Volumetric Keepout Regions

    System Bus Design Guidelines Figure 31. Heatsink Volumetric Keepout Regions Figure 32. Motherboard Component Keepout Regions ® Intel 815 Chipset Platform Design Guide...

  • Page 67: Debug Port Changes

    Previously, test access port (TAP) signals used 2.5V logic, as is the case with the Intel Celeron processor in the PPGA package. Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors utilize 1.5V logic levels on the TAP.
  • Page 68 System Bus Design Guidelines This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 69: System Memory Design Guidelines

    GMCH without a stitching capacitor as long as the trace on the topside of the PCB is less than 200 mils. Note: Intel recommends that a parallel plate capacitor between VCC3.3SUS and GND be added to account for the current return path discontinuity (See decoupling section). Use one 0.01 F X7R capacitor per every five system memory signals that switch plane references.

  • Page 70: System Memory 2-Dimm Design Guidelines

    SCSB[3:2]# SCSB[1:0]# SRAS# SCAS# SWE# SBS[1:0] SMAA[7:4] SMAB[7:4]# SDQM[7:0] SMD[63:0] SMB_CLK SMB_DATA DIMM 0 & 1 ® Intel Notes: Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB sys_mem_conn_2DIMM 815 Chipset Platform Design Guide...

  • Page 71: System Memory 2-Dimm Layout Guidelines

    In addition to meeting the spacing requirements outlined in Table 18, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge. ® Intel 815 Chipset Platform Design Guide Trace Lengths (inches) Spacing Min.

  • Page 72: Figure 37. System Memory Routing Example

    System Memory Design Guidelines Figure 37. System Memory Routing Example Routing in this figure is for example purposes only. It does not necessarily represent complete and NOTE: correct routing for this interface. sys_mem_routing_ex ® Intel 815 Chipset Platform Design Guide...

  • Page 73: System Memory 3-Dimm Design Guidelines

    8 MB Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB 82815 SMAA[12:8,3:0] DIMM_CLK[3:0] CK815 DIMM_CLK[7:4] DIMM_CLK[11:8] ® Intel 815 Chipset Platform Design Guide Double-Sided, Unbuffered Pinout without ECC SCSA[5:4]# SCSA[3:2]# SCSA[1:0]# SCKE[1:0] SCKE[3:2] SCKE[5:4] SCSB[5:4]# SCSB[3:2]# SCSB[1:0]# SRAS#...

  • Page 74: System Memory 3-Dimm Layout Guidelines

    SCKE[1:0] SMD[63:0] SDQM[7:0] SCAS#, SRAS#, SWE# SBS[1:0], SMAA[12:8,3:0] Trace Lengths (inches) Min. Max. Min. Max. Min. Max. Min. 1.75 ® Intel 815 Chipset Platform Design Guide DIMM 0 DIMM 1 DIMM 2 sys_mem_3DIMM_routing_topo Max. Min. Max. Min. Max. Min. Max.

  • Page 75: System Memory Decoupling Guidelines

    2 or layer 3 depending on stack-up. The filled region in the middle of the GMCH indicates a ground plate (on layer 1 if the power plane is on layer 2 or on layer 4 if the power layer is on layer 3). ® Intel 815 Chipset Platform Design Guide System Memory Design Guidelines...

  • Page 76: Figure 40. Intel ® 815 Chipset Platform Decoupling Example

    SDRAM signals. Capacitors should be placed between the DIMM connectors and evenly spread out across the SDRAM interface. For debug purposes, four or more 0603 capacitor sites should be placed on the backside of the board, evenly distributed under the Intel 815 chipset platform’s system memory interface signal field. ®...

  • Page 77: Compensation

    A system memory compensation resistor (SRCOMP) is used by the GMCH to adjust the buffer characteristics to specific board and operating environment characteristics. Refer to the Intel Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for details on compensation.
  • Page 78 System Memory Design Guidelines This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 79: Agp/Display Cache Design Guidelines

    For the detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms) refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide focuses only on specific Intel 815 chipset platform recommendations and covers both standard add-in card AGP and down AGP solutions.

  • Page 80: Graphics Performance Accelerator (Gpa)

    AGP video cards, display cache (for integrated graphics) must be populated on a card in the universal AGP slot. The card is called a Graphics Performance Accelerator (GPA) card. Intel provides a specification for this card in a separate document (Graphics Performance Accelerator Specification).

  • Page 81: Figure 42. Agp Left-Handed Retention Mechanism

    Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification. In addition, Intel has defined a reference design of a mechanical device to utilize the features defined in ECR #48.

  • Page 82: Agp 2.0

    AGP/Display Cache Design Guidelines ECR #48 can be viewed on the Intel Web site at: http://developer.intel.com/technology/agp/ecr.htm More information regarding this component (AGP RM) is available from the following vendors. Resin Color Black Green AGP 2.0 The AGP Interface Specification, Revision 2.0 enhances the functionality of the original AGP Interface Specification, Revision 1.0 by allowing 4X data transfers (4 data samples per clock) and...

  • Page 83: Agp Interface Signal Groups

    The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals) will be addressed separately. ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines Signal CLK (3.3V), RBF#, WBF#, ST[2:0], PIPE#, REQ#, GNT#, PAR,...

  • Page 84: Standard Agp Routing Guidelines

    Guidelines for short AGP interfaces (e.g., < 6 inches) and long AGP interfaces (e.g., > 6 inches and < 7.25 inches) are documented FRAME# IRDY# TRDY# STOP# DEVSEL# ® Intel 815 Chipset Platform Design Guide...

  • Page 85: Flexible Motherboard Guidelines

    20 mils 5-mil trace 15 mils 5-mil trace 20 mils 5-mil trace 15 mils ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines 2X/4X signal 2X/4X signal AGP STB# AGP STB 2X/4X signal 2X/4X signal STB/STB# length Associated AGP 2X/4X data signal length Min.

  • Page 86: Agp-Only Motherboard Guidelines

    (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 20 mils of space (1:4) ® Intel 815 Chipset Platform Design Guide...

  • Page 87: Agp Routing Guideline Considerations And Summary

    2. These guidelines apply to board stack-ups with 15% impedance tolerance. 3. 4 inches is the maximum length for a flexible motherboards. 4. Solution valid for AGP-only motherboards. ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines Max. Trace Spacing Length...

  • Page 88: Agp Clock Routing

    AGP interface of the GMCH. The following guidelines are not intended to replace thorough system validation for products based on the Intel 815 chipset platform. A minimum of six 0.01 F capacitors are required and must be as close as possible to the GMCH.

  • Page 89: Agp Routing Ground Reference

    AGP signals be reference to ground, depending on board layout. In an ideal design, the entire AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815 chipset platform for use with the universal socket 370.

  • Page 90: Agp Down Routing Guidelines

    This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than ±0.2 inch (i.e., a strobe and its complement must be the same length, within 0.2 inch). ® Intel 815 Chipset Platform Design Guide...

  • Page 91: Agp Routing Guideline Considerations And Summary

    Domain Set 3 NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils. ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines Length: 0.5" - 6.0" Width to spacing: 1:3 Strobe-to-Data Mismatch: ±0.5"...

  • Page 92: Agp Clock Routing

    AGP signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815 chipset platform.

  • Page 93: Agp 2.0 Power Delivery Guidelines

    AGP VREF generation must be considered together. Before developing VDDQ generation circuitry, refer to both the above requirements and the AGP 2.0 Interface Specification. ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines VDDQ (supplied by MB) 1.5V...

  • Page 94: Figure 46. Agp Vddq Generation Example Circuit

    FET. The source of the FET is connected to 3.3V. to 3.1V. When an ATX power supply is used, the of 34 m . ) to VDDQ. Intel +3.3V VDDQ 47 µF 220 µF 301 - 1% 1.21 k - 1% AGP_VDDQ_gen_ex_circ ® 815 Chipset Platform Design Guide...

  • Page 95: Vref Generation For Agp 2.0 (2X And 4X)

    Figure 47. ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines VREF from the graphics controller to the chipset VREF from the chipset to the graphics controller...

  • Page 96: Figure 47. Agp 2.0 Vref Generation And Distribution

    (See note 2) TYPEDET# VrefGC mosfet VrefCG +12V (See note 2) TYPEDET# VrefGC mosfet VrefCG Intel VDDQ 500 pF VDDQ GMCH 0.1 uF 500 pF VDDQ 500 pF VDDQ GMCH 0.1 uF 500 pF agp_2.0ref_gen_dist ® 815 Chipset Platform Design Guide...

  • Page 97: Additional Agp Design Guidelines

    The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept to less than 0.1 inch to avoid signal reflections from the stub. ® Intel 815 Chipset Platform Design Guide AGP/Display Cache Design Guidelines RBF# PIPE#...

  • Page 98: Agp Signal Voltage Tolerance List

    To maximize add-in flexibility, it is highly advisable to implement the universal connector in a system based on the Intel 815 chipset platform. All add-in cards are either 3.3V or 1.5V cards. The 4X transfers at 3.3V are not allowed due to timings.

  • Page 99: Agp / Display Cache Shared Interface

    AGP interface detailed in previous sections, the customer can choose to populate the AGP slot in a system based on the Intel 815 chipset platform with either an AGP graphics card, with a GPA card to enable the highest-possible internal graphics performance, or with nothing to get the lowest-cost internal graphics solution.

  • Page 100: Display Cache Clocking

    The capacitor should be placed as close as possible to the GMCH LRCLK pin. To minimize skew variation, Intel recommends a 1% series termination resistor and a 5% NP0 (also known as C0G) capacitor, to stabilize the value across temperatures. In addition to the 15 , 1% resistor and the 15 pF, 5% NP0 capacitor.

  • Page 101: Integrated Graphics Display Output

    100 MHz. The LC pi-filter is designed to filter glitches produced by the RAMDAC while maintaining adequate edge rates to support high-end display resolutions. ® Intel 815 Chipset Platform Design Guide Integrated Graphics Display Output resistance. One 75 resistance is from the DAC output to...

  • Page 102: Figure 49. Schematic Of Ramdac Video Interface

    Diodes D1, D2: Schottky diodes LC filter capacitors, C1, C2: 3.3 pF Ferrite bead, FB: 7 @ 100 MHz (Recommended part: Murata BLM11B750S) Coax Cable Zo = 75 Display Green Video connector Blue display_RAMDAC_video_IF ® 815 Chipset Platform Design Guide...

  • Page 103: Reference Resistor (Rset) Calculation

    The routing for these signals should be as similar as possible (i.e., same routing layer(s), same number of vias, same routing length, same bends, and jogs). ® Intel 815 Chipset Platform Design Guide Integrated Graphics Display Output (two 75 in parallel; one 75...

  • Page 104: Figure 51. Recommended Ramdac Component Placement & Routing

    An example is: Intel Place pi filter near VGA connector routes route Pi filter routes route Pi filter routes route Pi filter Avoid routing toggling signals in this shaded area RAMDAC comp placement routing ® 815 Chipset Platform Design Guide...

  • Page 105: Ramdac Layout Recommendations

    To minimize this, the following is required: Add external buffers to HSYNC and VSYNC. Examples include: Series 10 ® Intel 815 Chipset Platform Design Guide IREF ball/pin Short, wide route connecting resistor to IREF pin Resistor for setting RAMDAC reference current...

  • Page 106: Digital Video Out

    (if required). These signals are part of one of the GMCH XOR chains. C is a two-wire communications bus/protocol. The protocol and bus ® Intel 815 Chipset Platform Design Guide C interface, by means of the C cycles.

  • Page 107: Hub Interface

    NAND Tree testing. Each signal should be routed such that it meets the guidelines documented for its signal group. Figure 53. Hub Interface Signal Routing Example NAND tree test point HL11 ® Intel 815 Chipset Platform Design Guide HL_STB HL_STB# HL[10:0] GCLK CLK66 Clocks Hub Interface...

  • Page 108: Data Signals

    0.01 F capacitor located close to the component HREF pin. If the reference voltage is generated locally, the bypass capacitor must be close to the component HREF pin. to a maximum of 1 k (300 shown in example). ® Intel 815 Chipset Platform Design Guide...

  • Page 109: Compensation

    Compensation Independent hub interface compensation resistors are used by the GMCH and ICH to adjust buffer characteristics to specific board characteristics. Refer to the Intel Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet ®...
  • Page 110 Hub Interface This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 111: I/O Subsystem

    IDE channels. The ICH has integrated the series resistors that typically have been required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. Intel does not anticipate requiring additional series termination, but OEMs should verify the motherboard signal integrity via simulation.

  • Page 112: Figure 56. Ide Minimum/Maximum Routing And Cable Lengths

    Figure 56. IDE Minimum/Maximum Routing and Cable Lengths Figure 57. Ultra ATA/66 Cable 8 in. max. Traces 5-12 in. connector Black wires: ground Grey wires: signals Intel 10-18 in. 4-6 in. IDE_routing_cable_len IDE connector ATA66_cable ® 815 Chipset Platform Design Guide...

  • Page 113: Cable Detection For Ultra Ata/66

    Ultra DMA mode up to the highest transfer mode supported by both the chipset and the IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33). ® Intel 815 Chipset Platform Design Guide I/O Subsystem...

  • Page 114: Host Side Cable Detection

    To secondary IDE connector GPIO GPIO To secondary IDE connector GPIO GPIO 40-conductor cable 15 k 80-conductor IDE cable 15 k ® Intel 815 Chipset Platform Design Guide IDE Drive 10 k PDIAG IDE Drive 10 k PDIAG Open IDE_cable_det_host...

  • Page 115: Device Side Cable Detection

    BIOS when it sends the IDENTIFY_DEVICE packet during system boot, as described in the ATA/66 specification. Figure 59. Drive-Side IDE Cable Detection 0.047 µF 0.047 µF ® Intel 815 Chipset Platform Design Guide IDE Drive 10 k 40-conductor cable PDIAG 10 k...

  • Page 116: Primary Ide Connector Requirements

    PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification). 5.6 k 8.2 k ® Intel 815 Chipset Platform Design Guide 22 - 47 Reset# 10 k CSEL Pin 32 N.C.

  • Page 117: Secondary Ide Connector Requirements

    DD7. It is recommended that a host have a 10 k pull-down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification). ® Intel 815 Chipset Platform Design Guide 10 k 8.2 k I/O Subsystem 22 - 47...

  • Page 118: Layout For Both Host-Side And Device-Side Cable Detection

    Layout for Both Host-Side and Device-Side Cable Detection The Intel 815 chipset platform (using the ICH) can use two methods to detect the cable type. Each mode requires a different motherboard layout. It is possible to lay out for both host-side and device-side cable detection and decide the method to be used during assembly.

  • Page 119: Ac'97 Routing

    The ICH implements an AC’97 2.1-compliant digital controller. Any codec attached to the ICH AC-link must be AC’97 2.1 compliant as well. Contact your codec IHV for information on 2.1- compliant products. The AC’97 2.1 specification is available on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The ICH supports the codec combinations listed in Table 27.
  • Page 120 To provide wake capability and/or caller ID, standby power must be provided to the modem codec. If no codec is attached to the link, internal pull-downs will prevent the inputs from floating. Therefore, external resistors are not required. ® Intel 815 Chipset Platform Design Guide...

  • Page 121: Ac'97 Signal Quality Requirements

    The ICH provides internal weak pull-downs. Therefore, the motherboard does not need to provide discrete pull-down resistors. PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction of a pop when powering the mixer up or down. ® Intel 815 Chipset Platform Design Guide I/O Subsystem...

  • Page 122: Using Native Usb Interface

    (to ground) for each USB between the differential signal USB twisted-pair cable impedance. Note that the twisted- is the series impedance of both wires, which results in impedance. The trace impedance can be controlled by ® Intel 815 Chipset Platform Design Guide...

  • Page 123: I/O Apic (I/O Advanced Programmable Interrupt Controller)

    PICCLK requires special implementation for universal motherboard designs. See Section 4.2.9 Connect PICD0 to 2.5V through 10 k resistors. Connect PICD1 to 2.5V through 10 k resistors. ® Intel 815 Chipset Platform Design Guide Motherboard trace 47 pF 15 k Motherboard trace 47 pF...

  • Page 124: Smbus

    2 PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair. Based on simulations performed by Intel, a maximum of 4 PCI slots should be connected to the ICH. This limit is due to timing and loading considerations established during simulations. If a system designer wants 5 PCI slots connected to the ICH, then the designer’s company should...

  • Page 125: Lpc/Fwh

    NOGO signal asserted when booting from a PCI ROM. Note that it is not possible to boot from a ROM behind the Intel 82380AB. After booting from the PCI card, one potentially could program the FWH in circuit and program the ICH CMOS.

  • Page 126: Rtc Crystal

    C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain 32.768 kHz. 32768 Hz Xtal 0.047 µF 18 pF 18 pF ® Intel 815 Chipset Platform Design Guide VCCRTC RTCX2 10 M RTCX1 10 M VBIAS VSSRTC...

  • Page 127: Rtc Layout Considerations

    A standby power supply should be used to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy. ® Intel 815 Chipset Platform Design Guide VCC3_3SBY VccRTC 1.0 µF...

  • Page 128: Rtc External Rtcreset Circuit

    G3, and correspondingly prevents ICCRTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull-down. VCC3_3SBY Diode / battery circuit 1.0 µF 8.2 k 2.2 µF RTC_RTCRESET_ext_circ ® Intel 815 Chipset Platform Design Guide Vcc RTC RTCRESET...

  • Page 129: Rtc Routing Guidelines

    Excessive noise on VBIAS can cause the ICH internal oscillator to misbehave or even stop completely. To minimize the VBIAS noise, it is necessary to implement the routing guidelines described previously as well as the required external RTC circuitry. ® Intel 815 Chipset Platform Design Guide I/O Subsystem...
  • Page 130 I/O Subsystem This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 131: Clocking

    Clocking For an Intel 815 chipset platform, there are two clock specifications. One is for a 2-DIMM solution, and the other is for a 3-DIMM solution. In both specifications only single-ended clocking is supported. Intel 815 chipset platforms using a future 0.13 micron socket 370 processors cannot implement differential clocking.

  • Page 132: Figure 68. Platform Clock Architecture (2 Dimms)

    PCI total of 6 PCI 3 PCI 4 devices (µATX ) PCI 5 5 slots + 1 down PCI 6 PCI 7 Intel Processor Host unit Mem ory GM CH unit Hub I/F 32.768 kHz clk_arch_2DIMM ® 815 Chipset Platform Design Guide...

  • Page 133: 3-Dimm Clocking

    APIC clocks 48 MHz clocks 3V, 66 MHz clocks REF clock The following bullets list the features of the Intel CK-815 clock generator: Thirteen copies of SDRAM clocks Two copies of PCI clock One copy of APIC clock One copy of 48 MHz USB clock (3.3V) (non-SSC) (type 3 buffer) One copy of 48 MHz DOT clock (3.3V) (non-SSC) (see DOT details)

  • Page 134: Figure 69. Universal Platform Clock Architecture (3 Dimms)

    PCI 1 PCI 1 to zero delay Intel Processor Host I/F AGIP / local m em ory GM CH System m em ory Hub I/F 66/266 I/O Controller Hub PCI slots / down clk_arch_3DIMM ® 815 Chipset Platform Design Guide...

  • Page 135: Clock Routing Guidelines

    Layout 2 CK815 Layout 3 CK815 CK815 Layout 4 CK815 Layout 5 CK815 ® Intel 815 Chipset Platform Design Guide Section 1 Section 2 Section 1 Section 2 10 pF Section 1 Section 2 Section 0 Section 1 Section 3...

  • Page 136: Table 30. Simulated Clock Routing Solution Space

    A + 3.5” – L1 0.5” A + 5.2” A + 8” A + 8” A + 8” A + 8” A + 3” A + 4” A + 8.5” A + 14” A + 5” A + 11” 815 Chipset Platform Design Guide...

  • Page 137: Clock Decoupling

    370-pin socket, or pull-up resistors on the motherboard. While SEL0 is a pure input to a Intel CK-815-compliant clock driver, REF0 is also the 14 MHz output that drives the ICH and other devices on the platform. In addition to sampling BSEL[1:0] at reset, Intel CK-815-compliant clock drivers are configured by the BIOS via a two-wire interface to drive SDRAM clock outputs at either 100 MHz (default) or 133 MHz (if all system requirements are met).

  • Page 138: Clock Skew Assumptions

    1.0). Motherboard clock routing must account for this additional electrical length. Therefore, AGPCLK routed to the connector must be shorter than HLCLK to the GMCH, to account for this additional 750 ps. ® Intel 815 Chipset Platform Design Guide Notes...

  • Page 139: Intel ® Ck-815 Power Gating On Wake Events

    For systems providing functionality with future 0.13 micron socket 370 processors, special handling of wake events is required. When a wake event is triggered, the GMCH and the Intel CK- 815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by...
  • Page 140 Clocking This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 141: Power Delivery

    Derived power rail Dual power rail Figure 71 shows a power delivery architecture example for a system based on the Intel 815 chipset platform. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the suspend-to-RAM (STR) state. During STR, only the necessary devices are powered.

  • Page 142: Figure 71. Power Delivery Map

    Total max. power dissipation for GMCH = 4 W. Total max. power dissipation for AC'97 = 15 W. In addition to the power planes provided by the ATX power supply, an instantly available Intel 815 chipset platform (using Suspend-to-RAM) requires six power planes to be generated on the board.
  • Page 143 Dual plane. On the CRB, the only devices connected to the 5V Dual plane are voltage regulators (to regulate to lower voltages). Note: This switch is not required in an Intel 815 chipset platform that does not support Suspend-to-RAM (STR).

  • Page 144: Thermal Design Power

    Engineering judgment should be used to determine the optimal value. This determination can include cost concerns, commonality considerations, manufacturing issues, specifications, and other considerations. ® 815 Chipset Family: 82815 Graphics and Memory Controller ® Intel 815 Chipset Platform Design Guide...

  • Page 145: Atx Power Supply Pwrgood Requirements

    S3 state. System designers should insure that PWROK signal designs are glitch free. ® Intel 815 Chipset Platform Design Guide MIN) / I LEAKAGE MAX) / I may not be meaningful.

  • Page 146: Power Management Signals

    For an ATX power supply, when PSON is low, the core wells are turned on. When PSON is high, the core wells from the power supply are turned off. ® Intel 815 Chipset Platform Design Guide...

  • Page 147: Power Button Implementation

    All lights, except a power state light, must be off. The system must be inaudible: silent or stopped fan, drives off. Note: Contact Microsoft for the latest information concerning PC9x or PC200x and Microsoft Logo programs. ® Intel 815 Chipset Platform Design Guide Power Delivery...

  • Page 148: V/3.3V Power Sequencing

    SLP_S3# SLP_S5# SUS_STAT# Vcc3.3core CPUSLP# PWROK Clocks PCIRST# Cycle 1 from GMCH Cycle 1 from ICH Cycle 2 from GMCH Cycle 2 from ICH STPCLK# Freq straps CPURST# Clocks invalid ® Intel 815 Chipset Platform Design Guide Clocks valid pwr_G3-S0_trans...

  • Page 149: Figure 74. S0-S3-S0 Transition

    Cycle 2 from GMCH Cycle 2 from ICH CPURST# SLP_S3# SLP_S5# PWROK Vcc3.3core Clocks Freq straps Wake event ® Intel 815 Chipset Platform Design Guide DRAM in STR (CKE low) DRAM active Clocks valid Clocks invalid Power Delivery DRAM active Clocks valid pwr_S0-S3-S0_trans...

  • Page 150: Figure 75. S0-S5-S0 Transition

    Cycle 2 from GMCH Cycle 2 from ICH CPURST# SLP_S3# SLP_S5# PWROK Vcc3.3core Clocks Freq straps Wake event DRAM in STR (CKE low) DRAM active Clocks valid Clocks invalid ® Intel DRAM active Clocks valid pwr_S0-S5-S0_trans 815 Chipset Platform Design Guide...

  • Page 151: Table 33. Power Sequencing Timing Definitions

    PWROK inactive to Vcc3.3core not good Wake event to SLP_S3# inactive PCIRST# inactive to STPCLK# inactive SLP_S3# active to SLP_S5# active SLP_S5# inactive to SLP_S3# inactive ® Intel 815 Chipset Platform Design Guide Parameter Power Delivery Min. Max. Units RTC clocks...

  • Page 152: Vddq/Vcc1_85 Power Sequencing

    3.3V supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.85V logic is powered up. Some signals that are defined as “Input-only” actually have 3.3V SHDN IPOS INEG GATE COMP vddq_pwr_seq ® Intel 815 Chipset Platform Design Guide...

  • Page 153: Figure 77. Example 1.85V/3.3V Power Sequencing Circuit

    If one of these signals goes high while one of its associated power planes is active and the other is not, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging, internal currents. ® Intel 815 Chipset Platform Design Guide +3.3V Power Delivery +1.8V...

  • Page 154: V/V5Ref Sequencing

    USBOC. If these signals are not needed during suspend, V5REF_Sus can be hooked to the VCCSus3_3 rail. Figure 78. 3.3V/V5REF Sequencing Circuitry Vcc Supply (3.3V) To System 5V Supply 1.0 uF To System ® Intel 815 Chipset Platform Design Guide vref_circuit...

  • Page 155: System Design Checklist

    This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an Intel 815 chipset platform for use with the universal socket 370. This is not a complete list and does not guarantee that a design will function properly. For items other than those in the following text, refer to the latest revision of the design guide for more- detailed instructions regarding motherboard design.

  • Page 156: Cmos Checklist

    3.3V. Connect to PWRGOOD logic such that a logic Low on BSEL0 negates PWRGOOD. pull-up resistor to 3.3V. Connect to Intel CK-815 REF pin via 10 k series resistor. Connect to GMCH LMD13 pin via 10 k ®...
  • Page 157 VTTPWRGD VREF [6:0] ® Intel 815 Chipset Platform Design Guide Recommendations Connect to divider on VCC2.5 or VCC3.3 to create 1.25V reference with a 4.7 F decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VTT as source voltage for this reference! Tie to ground.

  • Page 158: Gmch Checklist

    Pull-down to ground through 8.2 k Connect to PCI connector 0 device Ah. / Connect to PCI connector ® 1 device Bh. / Connect to Intel 82559 LAN (if implemented). Connect to AGP voltage regulator circuitry / AGP reference circuitry.

  • Page 159: Designs That Do Not Use The Agp Port

    GNT# GPAR AD_STB[1:0] SB_STB AD_STB[1:0]# SB_STB# ST[2:0] ® Intel 815 Chipset Platform Design Guide System Design Checklist Pull-up / Pull-Down Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ...

  • Page 160: System Memory Interface Checklist

    GMCH are used. (0,1 for DIMM0; 2, 3 for DIMM1; 4,5 for DIMM2) ® Connect to GND (since the Intel 815 chipset platform does not support registered DIMMS). Add a 4.7 kΩ pull-up resistor to 3.3V. This recommendation write-protects the DIMM’s EEPROM.

  • Page 161: Ich Checklist

    Pull-up through 8.2 k resistor to VCC3_3 ® Signal coming from Intel CK-815 device pass through a 33 Ω resistor to PCI connector. Signal comes from buffered PCIRST# Pull-up through 8.2 kΩ resistor to VCC3_3 Passes through 33 Ω resistor Pull-up through 5.6 kΩ...

  • Page 162: Usb Checklist

    Decouple through a 47 pF capacitor to GND Signal goes through 15 Ω resistor Pull-down through a 15 kΩ resistor to GND Connected to AGP/AC97 Circuitry (See Intel CRB Schematic pg. 20) Pull-down through a 15 kΩ resistor to GND Use 15 series resistors.

  • Page 163: Ide Checklist

    LAD[3..0]#/FWH[3..0]# SPKR AC_SDOUT, AC_BITCLK AC_SDIN[1:0] ® Intel 815 Chipset Platform Design Guide Recommendations Connect from ICH to IDE Connectors. No external series termination resistors required on those signals with integrated series resistors. Pull-down through a 10 k resistor to GND.
  • Page 164 3VSB (3 V standby) on both of these signals. No external pull-ups are required on PCI_GNT# signals. However, if external pull-ups are implemented, they must be pulled up to 3.3V. ® Intel 815 Chipset Platform Design Guide resistors are 1% or 2% (or 39...

  • Page 165: Lpc Checklist

    PDR3, PDR4, PDR5, PDR6, PDR7 SYSOPT ® Intel 815 Chipset Platform Design Guide Recommendations Pull-up through 8.2 k resistor to VCC3_3 Pull-up through 8.2 kΩ resistor to VCC3_3. Do not connect LPC PME# to PCI PME#. If the design requires the Super I/O to support wake from any suspend state, connect Super I/O LPC_PME# to a resume well GPI on the ICH.

  • Page 166: System Checklist

    Pull-down through a 8.2 kΩ resistor to GND Pull-down to GND FWH INIT# must be connected to processor INIT#. FWH RST# must be connected to PCIRST#. For a system with only one FWH device, tie ID[3:0] to ground. ® Intel 815 Chipset Platform Design Guide...

  • Page 167: Clock Synthesizer Checklist

    MEMCLK7/DRAM_7, SCLK VCC3.3 ® Intel 815 Chipset Platform Design Guide Recommendations Connects to R-RefCLK, USB_CLK, SIO_CLK14, and ICHCLK14. Passes through 33 Ω resistor Passes through 33 Ω resistor When signal is input for ICH it is pulled down through a 18 pF capacitor to Passes through 33 Ω...

  • Page 168: Lan Checklist

    82559. Jumper to VCC3SBY through 330 Ω resistor Use plane for this signal. Pull-up through 330 Ω resistor to VCC3SBY Pass through 100 Ω resistor to AD20 from Intel 82559 pin IDSEL. Recommendations Consider all loads on a regulator, including other regulators.

  • Page 169: Power

    (3.3V) To System ® Intel 815 Chipset Platform Design Guide Recommendations The power pins should be connected to the proper power plane for the processor ‘s CMOS compatibility signals. Use one 0.1 F decoupling capacitor. No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a GPI, or use a safemode strapping for Clear CMOS Requires six 0.1 F decoupling capacitors...
  • Page 170 System Design Checklist This page is intentionally left blank. ® Intel 815 Chipset Platform Design Guide...

  • Page 171: Third-Party Vendor Information

    Intel 815 chipset platform for use with the universal socket 370. The list of vendors can be used as a starting point for the designer. Intel does not endorse any one vendor, nor guarantee the availability or functionality of outside components.
  • Page 172 Eileen Carlson [eileen.carlson@conexant.com] (858) 713-3203 Bill Schillhammer [billhammer@focusinfo.com] (978) 661-0146 Marcus Rosin [marcus.rosin@philips.com] Greg Davis[gdavis@ti.com] (214) 480-3662 Chi Tai Hong [cthong@chrontel.com] (408) 544-2150 Creg Davis[gdavis@ti.com] (214) 480-3662 387R Jason Lu [Jason.Lu@nsc.com] (408) 721-7540 ® Intel 815 Chipset Platform Design Guide...

  • Page 173: Appendix A: Customer Reference Board (Crb)

    Appendix A: Customer Reference Board (CRB) Appendix A: Customer Reference Board (CRB) This section provides a set of Customer Reference Board (CRB) schematics for the Intel 815 chipset platform for use with the universal socket 370. ® Intel 815 Chipset Platform Design Guide...
  • Page 174 6, 7, 8 Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel...

  • Page 175: Block Diagram

    FirmWare Hub Keyboard Floppy Game Port Mouse Serial 1 Parallel Serial 2 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD BLOCK DIAGRAM Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 176 VTT1_5 VTT1_5 VTT1_5 AN21 VTT1_5 AA35 VTT1_5 AA33 VTT1_5 VTT1_5 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD 370-PIN SOCKET, PART 1 Platform Apps Engineering Last Revision Date: int e l 3-26-01 1900 Prairie City Road Sheet: Folsom, CA 95630 REV.
  • Page 177 RTTCTRL VCOREDET JP29 JUMPER R322 R323 56, %1 110, %1 GTLREF0 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD GTLREF 6 R347 Do not stuff R347 370-PIN SOCKET, PART 2 C482 GTLREF0 to CPU. Platform Apps Engineering 0.1UF GTLREF to GMCH.
  • Page 178 VDD2_5[0] L_VCC2_5 VDD2_5[1] C102 C101 C100 VSS2_5[1] 0.001uF 0.1uF 4.7uF VSS2_5[0] Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD CLOCK SYNTHESIZER Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 APICCLK_CPU R338 R339 MOSFET N 4,7,31 TUAL5...
  • Page 179 VDDQ NOTE: VCC1_8 IS A NOMINAL 1.85V VDDQ VDDQ AF24 AE25 82815 GMCH Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD 82815 GMCH: HOST INTERFACE Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 82815 GMCH AA23...

  • Page 180: Memory Interface

    SM_MD59 SMD59 SM_MD60 SMD60 SM_MD61 SMD61 SM_MD62 SMD62 SM_MD63 SMD63 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD 82815 GMCH: SYSTEM MEMORY Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 181 0.1uF 18pF of clock ball (AA21). GMCH and via straight to plane. Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD 82815 GMCH: GRAPHICS Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date:...

  • Page 182: Agp Connector

    GSTOP# 8 PCI_PME# 12,16,17,29 CON_AGPREF GPAR 200 1% TYPEDET# 2N7002LT1 GCBE#0 ADSTB0# CONN_AGPREF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD AGP CONNECTOR Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...

  • Page 183: System Memory

    VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 SAO_PU SAO_PU System Memory DIMM0 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SYSTEM MEMORY: DIMM0 Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 184 VSS4 VSS3 VSS2 VSS1 VCC3SBY SAO_PU 2.2k SAO_PU System Memory: DIMM1 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SYSTEM MEMORY: DIMM1 Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 185 REQ4# RESV2RD R212 HL11 R173 8.2K Don't Stuff R173 For Test/Debug Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD ICH, PART 1 Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 186 30,31,35 PWROK SDD13 SDD14 SDD14 SDD15 Empty SDD15 Debug Only Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD ICH, PART 2 Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 VCC3_3 ICH_PWROK 741G08 AND REV. Last Revision Date:...
  • Page 187 LAD0/FWH0 LAD0/FWH0 13,15 FWH_ID0 FWH_ID1 FWH_ID2 FWH_ID3 RP68 RP68 for Test/Debug Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD FIRMWARE HUB (FWH) Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 188 KEYLOCK# SIO_GP21 SIO_GP22 SYSOPT Pulldown on SYSOPT for IO address of 0x02E R224 4.7K Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SUPER I/O Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date:...

  • Page 189: Pci Connector

    SBOP2 SBOP2 12,17,29 AD15 AD13 AD11 C_BE#0 C_BE#0 12,17,29 PU2_REQ64# PU2_REQ64# Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD PCI CONNECTOR 0 Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 190 STOP# 12,16,29,36 SDONEP3 SBOP3 36 12,16,29 C_BE#0 12,16,29 JP25 16,29 PERR# PU3_REQ64# Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD PCI CONNECTOR 1 Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 C368 C414 C415 0.1UF 0.1UF 0.1UF...

  • Page 191: Ide Connectors

    R130 R132 0.047UF 5.6K VCC3_3 R191 8.2K U11C PCIRST_BUF# PCIRST_BUF# SN74LVC07A Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD ULTRA DMA/66 CONNECTOR Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 192 USB_GND_C FB10 USB_PO_D USB_GND_D FB11 USB_GND_A 100UF C342 100UF C343 47PF 100UF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD USB HUB Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...

  • Page 193: Parallel Port

    J8_9 J8_8 J8_7 J8_6 J8_5 J8_17 J8_4 J8_16 J8_3 J8_2 J8_14 J8_1 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD PARALLEL PORT Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 194 100PF 100PF PLACE CLOSE TO HEADER C347 C350 C344 100PF 100PF 100PF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SERIAL PORTS Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 195 DRVDEN#1 INDEX# MTR#0 DS#0 DIR# STEP# WDATA# WGATE# TRK#0 WRTPRT# RDATA# HDSEL# DSKCHG# Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD KEYBOARD/MOUSE/FLOPPY Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 196 47PF 47PF The game port capacitors together and to SIO AVSS. Tie to system ground at only a single point. Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD GAME PORT Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 DB15 REV.
  • Page 197 6,9,12,14,15,16,17,18,19,29 5VFTSDA 5VFTSCL 3VFTSDA 8,25 3VFTSCL 8,25 SL_STALL FTHSYNC FTVSYNC Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD DIGITAL VIDEO OUT CONNECTOR Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...

  • Page 198: Vga Connector

    C188 3.3PF C185 C180 10PF 10PF C249 C208 10PF 10PF C211 3.3PF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD VIDEO CONNECTOR Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 199 GND[12] AC97_SDATA_IN1 AC_SDIN1 13,36 GND[13] AC97_SDATA_IN0 AC_SDIN0 13,27,36 GND[14] AC_BITCLK 13,27 AC97_BITCLK Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD AUDIO/MODEM RISER Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 200 AC_BITCLK_R R243 AC_BITCLK 13,26 EAPD R237 JP18 100K AUD_VREFOUT C356 22PF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD AC'97 AUDIO CODEC Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...

  • Page 201: Audio Connectors

    BYPASS LNLVL_L_R BYPASS SHUTDN R172 R113 LM4880 C321 EAPD C283 0.1UF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD AUDIO CONNECTORS Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 J6-4 HP30 HP29 HP28 HP27 HP26 DB15 AUD_STK...
  • Page 202 LAN_TEST TEST R205 TEXEC 4.7K RBIAS10 R201 RBIAS10 RBIAS100 RBIAS100 R202 VREF NC11 NC10 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 203 VCC3SBY R267 4.7K JP22 JP8_SMBC R266 L_SMBCLK VCC3SBY R268 4.7K JP23 JP9_SMBD R265 L_SMBD Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 204 1200UF 1200UF VCC 2.5 VOLTAGE REGULATOR NDS356AP VCC5 VOUT C111 LT1587ADJ SI4410DY 0.1UF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SI4410DY VOLTAGE REGULATORS Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 VCC5 VCC5DUAL R176 NPOP...
  • Page 205 C268_R156 R156 7.5K-1% 1UF-X7R 1UF-X7R 0.001UF 301-1% VDDQ_FB R161 1.21K-1% Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD AGP, VCMOS VOLTAGE REGULATOR Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 VDDQ C270 C242 C278 1UF-X7R 1UF-X7R 1UF-X7R REV.
  • Page 206 4700pF C449 C450 C451 820uF 820uF 1000uF 0.004 R335 C453 0.1uF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD VRM 8.5 Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 VCCVID REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 207 VCC3SBY VCC3SBY VCC3SBY CRa4 GP23LED GP26LED CRb4 SN74LVC07A SN74LVC07A 4.7K Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SYSTEM, PART 1 Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 VCC5 SPEAKER GPIO26_FPLED REV. Last Revision Date:...
  • Page 208 VCC3SBY U12C U12D ST69 RSMRST# 13,30 74LVC14A 74LVC14A R128 8.2k Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD SYSTEM, PART 2 Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 VCC2_5 PWRGOOD 4 R344 1.8k 13,30,31 REV.
  • Page 209 For Future Compatability Upgrade RTTCTRL 8.2K SLEWCTRL RP55 8.2K VCCRTC VCC5 RP52 8.2K R263 R262 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD PULLUP/PULLDOWN RESISTORS Platform Apps Engineering Last Revision Date: int e l 1900 Prairie City Road Sheet: Folsom, CA 95630 REV. 3-26-01...
  • Page 210 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF C471 C472 0.1UF 0.1UF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD DRAM, ICH, & GMCH DECOUPLING Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 REV. Last Revision Date: 3-26-01 Sheet:...
  • Page 211 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD VRM DECOUPLING Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 C474 C475 C476 C381 0.1UF 0.1UF 0.1UF 0.1UF...
  • Page 212 HL[10:0] 8,12 HLSTB 8,12 HLSTB# PROBE_CONNECTOR HUBREF 7,8,12 VCC1_8 HL10 P08-050-SL-A-G Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD HUB INTERFACE CONNECTOR Platform Apps Engineering Last Revision Date: int e l 3-26-01 1900 Prairie City Road Sheet: Folsom, CA 95630 REV.
  • Page 213 V1_8SB R349 R353 THERMTRIP# 1.6K VCC1_8 R350 R352 Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD Platform Apps Engineering int e l 1900 Prairie City Road Folsom, CA 95630 V3SB R351 PWRBTN# 13,34 THERMTRIP Last Revision Date: Sheet: REV. 3-26-01...

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