Cpcd - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.38.
CPCD
CPCD latched processor PCD pin
A latched version of the Pentium prooessor PCD output signal.
Output from 82496 Cache Controller (pin M01)
Synchronous to ClK
Signal Description
CPCD reflects the Pentium processor PCD output signal during a CPU cycle on the memory
bus. CPCD is inactive (LOW) during write-backs, snoop write-backs, and allocations.
CPCD can be used, along with CPWT, to distinguish between write hit to [S] state and write
miss cycles. In all cases PALLC# will be inactive (high). See Table 5-3.
Table 5-3. Using CPCD and CPWT to Determine Write Hit to
[5]
versus Write Miss
CPCD CPWT Cycle Type
0 0 Write Hit to IS]
0 1
Cacheable Write Miss (Non Allocatable Write Through)
1
x
Non Cacheable Write Miss
When Driven
CPCD is valid from the CLK of CADS# and SNPADS# until the CLK of CRDY# or CNA#.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CADS# Address and cycle specification signals (Le., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC,
CW/R#,
CWAY, KlOCK#, MAP, MBTI3:0]. MCACHE#,
MCFA, MSET, MTAG, NENE#, PAllC#, RDYSRC, and SMlN#) are valid with
CADS#.
5-80
I