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D/C - Intel 82496 CACHE CONTROLLER User Manual

Volume 2: 82496 cache controller and 82491 cache sram data book

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HARDWARE INTERFACE

5.2.2.44.

D/C#

D/C#

Data/Code

Cycle decode signal.

Output from Pentium processor (pin V04), Input to 82496 Cache Controller (pin

J15)

Synchronous to ClK

Signal Description

Refer to the Pentium™ Processor Data Book for a detailed description of this signal.

I

5-87

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82491 cache sram Pentium