Write-Through Cache Designs; Write-Back Cache Designs; 82496 Cache Controller Cache Consistency Protocol - Intel 82496 CACHE CONTROLLER User Manual

CHAPTER 3
COMPONENT OPERATION
This section presents the cache consistency protocol of the 82496 Cache Controller and
explains the architectural decisions underlying the design of the component.
Cache consistency protocols are designed to ensure that, in a shared memory system, cache
data and main memory data are consistent. A number of cache architectures can be employed
to maintain consistency, including write-through, posted write, write-back (also called copy-
back), and two-level mixed (primary write-through with secondary write-back). Write-through
and write-back designs are the most popular.
3.1. WRITE-THROUGH CACHE DESIGNS
In
write-through cache designs,.cache memory remains consistent with main memory. In a
write-through cache design, every CPU write operation accesses both cache memory and main
memory. A write-through cache must monitor bus masters other than the CPU that could alter
main memory locations. The cache must then render some of its contents invalid based on
these alterations. To maintain consistency, a write-through cache employs a valid/invalid
protocol. 'Valid' indicates that a cache tag contains a memory location which is unaltered from
main memory. 'Invalid' indicates that the tag is empty. The 82496 Cache Controller/82491
Cache SRAM can be implemented as a write-through cache by using available control signals
(ie. MWB/WT#, MKEN#). These control signals cause the tag state to use only the shared and
invalid MESI cache coherency protocol states.
3.2. WRITE-BACK CACHE DESIGNS
In write-back cache architectures, writes may be made to the cache exclusively. Modified
cache lines are subsequently written back into main memory. The "modified bit" associated
with each cache line is used by the cache controller to determine whether a specific main
memory locations needs to be updated.
The 82496 Cache Controller/82491 Cache SRAM employs such a write-back architecture.
In
addition, the 82496 Cache Controller/82491 Cache SRAM tracks data that can be shared by
multiple bus masters within a shared memory system. This additional tracking is accomplished
using the MESI protocol, wherein each cache line is classified as modified [M], exclusive [E],
shared [S], or invalid [I].
3.3. 82496 CACHE CONTROLLER CACHE CONSISTENCY
PROTOCOL
The 82496 Cache Controller/82491 Cache SRAM is designed to supplement the Pentium
processor with the cache and cache management resources needed to implement high-
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