Highz - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.54.
HIGHZ#
HIGHZ# High Impedance
Causes 82496 Cache Controller outputs to be tri-stated.
Configuration Input to 82496 Cache Controller (pin 005)
Synchronous to ClK
Signal Description
If SLFTST# is active while HIGHZ# is inactive during RESET, the 82496 Cache Controller
cache controller enters self-test. If SLFTST# and HIGHZ# are both sampled active during
RESET, the 82496 Cache Controller floats all 82496 Cache Controller output and I/O signals
until the next RESET. If SLFTST# is inactive, a nonnal initialization occurs. See TableS-5.
Table 5-5. Actions Based on 82496 Cache Controller Configuration Test Inputs
(HIGHZ# and SLFTST#)
HIGHZ# SLFTST# Action Taken by 82496 Cache Controller
1 0 Self-Test (BIST)
0 0 Outputs and
1/0
Floated (High-Z)
x 1 Normal Initialization (Reset)
When Sampled
HIGHZ# is sampled as shown in the Initialization and Configuration chapter. HIGHZ# is a
"don't care" until the 82496 Cache Controller/82491 Cache SRAM RESET sequence
completes with FSIOUT# going inactive, when it becomes the MBALE pin.
Relation to Other Signals
Pin Symbol Relation to Other Signals
RESET
HIGHZ# is sampled when RESET is active. Refer to Chapter 4 for specific timing
requirements with respect to RESET.
SlFTST# HIGHZ# and SlFTST# determine if either normal 82496 Cache Controller BIST is
executed or tri-state test mode is entered.
MBAlE
HIGHZ# shares a pin with MBAlE. 82496 Cache Controller outputs and
1/0
signals are tri-stated when HIGHZ# and SlFTST# are both sampled active during
RESET.
5-100
I