Mesi State Changes For Read Cycles: Cpu To 82496 Cache Controller; 82491 Cache Sram Caches - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
Table 3-8. MESI State Changes for READ Cycles: CPU to 82496 Cache Controller!
82491 Cache SRAM Caches
To To
Cache CPU
c---
P D C
W K
W
I A B E
T C C Initial I N Final
Initial # H Final CPU
State
Read
W
#
State
Memory
Cycle
State
E
State
Bus of
Only:
T of
Bus
Type of CPU #
of CPU Activity Cache Cache # Cache Activity
Locked 'X'
x x
1 I Read 'X'
x x x
Same Read
Not M,E,S
x x x
Same None M NO
x x
M None
Locked
I
x x
1
I Read M NO
x x
M None
N
0
t
e
s
1
5
5
I 1
x
0
S
LFIL M NO 1 0 M None 3,5
I 0 1 0 E LFIL M NO 1 0 M None 3
I 0 0 0 S LFIL M NO 1 0 M None 3,4,5
S
x x x
S None E
I
x x
1 I Read E
I
x x
0 S LFIL E
S
x x x
S
None
S
I
x x
1 I Read S
I
x
1 0 I Read S
I
x
1 0
S
LFIL
S
I
x
0 0 S LFIL S
I 1
x
1 I Read I
I 0
x
1 I Read I
I 1
x
0 S LFIL I
I 0
x
0 S LFIL I
I
x
0 0
S
LFIL I
I
x
1 0 I Read I
NOTES:
CPU refers to Pentium™ processor.
Cache refers to 82496 Cache Controller/82491 Cache SRAM.
LFIL
=
Line Fill
NO
x
NO
x
NO 0
x x
x x
YES
x
NO 0
x
0
x x
x x
NO 0
NO 0
YES 0
YES
x
Refer to Table 3-2 for 82496 Cache Controller state transition decisions.
3-20
x
E None
x
E None
0 E None 3
x
S
None
x
S None
1 S None 2
0
S
None
3
0 S None 3
x
S
LFIL
x
M,E,S LFIL
0 S LFIL
0 M,E,S LFIL
0
S
LFIL
6
1
S
LFIL
6
I