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Intr - Intel 82496 CACHE CONTROLLER User Manual

Volume 2: 82496 cache controller and 82491 cache sram data book
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i
ntel
®
HARDWARE INTERFACE
5.2.2.63.
INTR
INTR
Maskable Interrupt
Maskable interrupt request to the Pentium processor.
Input to Pentium processor (pin N18)
Asynchronous
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of this signal.
I
5-109

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