Brdyc2 - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.20. BRDVC2#
BRDYC2# Burst Ready Cache 2
Data input and output control signal.
Output from 82496 Cache Controller (pin G15) to 82491 Cache SRAM BRDYC#
Input
Synchronous to ClK
Signal Description
The 82496 Cache Controller burst ready output indicates to the 82491 Cache SRAM SRAMs
that the 82496 Cache Controller/82491 Cache SRAM cache subsystem has either presented
data to the CPU or accepted data from the CPU.
When Driven
BRDYC2# is driven during non-locked read hit cycles when data from the 82491 Cache
SRAM is read on the CPU bus. BRDYC2# is driven during write cycles when the 82491
Cache SRAM write buffer and/or 82491 Cache SRAM array is available to accept the write
data.
Relation to Other Signals
Pin Symbol Relation to Other Signals
BRDYC# (82491 BRDYC2# is connected to the 82491 Cache SRAM BRDYC# input.
Cache SRAM)
BRDYC1# BRDYC2# and BRDYC1# are logically equivalent.
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