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Intel 82496 CACHE CONTROLLER User Manual page 306

Volume 2: 82496 cache controller and 82491 cache sram data book
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Table of Contents

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HARDWARE INTERFACE
5.2.2.117.
RIS#
RIS#
RIS#
For use with Intel debug port.
Asynchronous Input
Internal Pull-up Resistor
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of this signal.
I
5-181

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