Pin States During Reset - Intel 82496 CACHE CONTROLLER User Manual

PINOUTS
Table 1-15. Pin States During RESET
State State
During During
Pin Name Part RESET Pin Name Part RESET
APCHK# Pentium™ processor High IU Pentium processor Low
APERR# 82496 Cache Controller High IV Pentium processor Low
APIC# 82496 Cache Controller Undefined KLOCK# 82496 Cache Controller High
BLE#
82496 Cache Controller Low
MAP 82496 Cache Controller Undefined
BP[3:2], Pentium processor Low MAPERR# 82496 Cache Controller High
BP/PM[1 :0] MBT[3:0] 82496 Cache Controller Low
BREQ Pentium processor Low MCACHE# 82496 Cache Controller Undefined
BT[3:0] Pentium processor Low MCFA[6:0] 82496 Cache Controller Undefined
CADS# 82496 Cache Controller High MDATA[7:0]
82491 Cache SRAM High-Z
CAHOLD 82496 Cache Controller Note 1 MHITM#
82496 Cache Controller High
CCACHE# 82496 Cache Controller Undefined MSET[10:0] 82496 Cache Controller Undefined
CD/C# 82496 Cache Controller Undefined MTAG[11:0] 82496 Cache Controller Undefined
CDTS# 82496 Cache Controller High MTHIT# 82496 Cache Controller High
CM/IO#
82496 Cache Controller Undefined NENE#
82496 Cache Controller Undefined
CPCD. 82496 Cache Controller Undefined PALLC#
82496 Cache Controller Undefined
CPWT 82496 Cache Controller Undefined PCHK# Pentium processor High
CSCYC 82496 Cache Controller Undefined PRDY Pentium processor Low
CW/R# 82496 Cache Controller Undefined RDYSRC 82496 Cache Controller Undefined
CWAY 82496 Cache Controller Undefined SMIACT# Pentium processor High
FERR# Pentium processor High SMLN# 82496 Cache Controller Undefined
FSIOUT# 82496 Cache Controller
Low
SNPADS# 82496 Cache Controller High
HIT# Pentium processor
High
SNPBSY# 82496 Cache Controller Low
HLDA Pentium processor Low SNPCYC# 82496 Cache Controller High
IBT Pentium processor Low TDO Pentium processor Note 2
IERR#
Pentium processor High
82496 Cache Controller
IPERR#
82496 Cache Controller
High 82491 Cache SRAM
NOTES:
1. The state of CAHOLD depends upon whether self-test is selected.
2. The state of TDO is determined by boundary scan which is independent of all other signals including
RESET.
Note that "Undefined" does not mean that the signal is floating. It means that the value being driven during
RESET will vary.
I
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