Intel 82496 CACHE CONTROLLER User Manual page 294

HARDWARE INTERFACE
2 N
N+l
MCLK
MSEL#
MZBTtI
MEOC/I
CDII88
NOTES:
1. In strobed mode, MZBT# is still sampled with respect to MSEL# and MEOC# as shown above;
however, MCLK is inactive.
2. The MZBT# value sampled on clock 2 is used for the first transfer that occurs in region A. The MZBT#
value sampled on clock n is used for the first transfer that occurs on any clock following clock n.
Figure 5-30. MZBT# Sampling
Relation to Other Signals
Pin Symbol Relation to Other Signals
MEOC# MZBT# is sampled with MSEL# and MEOC# and has no affect otherwise.
MSEL# MZBT# is sampled with MSEL# and MEOC# and has no affect otherwise.
MX4/8#
MZBT# shares a pin with the MX4/8# configuration input.
I
5-169