Table Of Contents - Intel 82496 CACHE CONTROLLER User Manual

TABLE OF CONTENTS
CHAPTER 1
PINOUTS Page
1.1. PINOUT DIAGRAMS .................................................................................................... 1-1
1.1.1. Pentium™ Processor Pinouts ................................................................................... 1-1
1.1.2. 82496 Cache Controller Pinouts ............................................................................... 1-3
1.1.3. 82491 Cache SRAM Memory Pinouts ...................................................................... 1-5
1.2. PIN CROSS REFERENCE TABLES ............................................................................. 1-7
1.2.1. Pentium Processor .................................................................................................... 1-7
1.2.2. 82496 Cache Controller ............................................................................................ 1-9
1.2.3. 82491 Cache SRAM ............................................................................................... 1-12
1.3. BRIEF PIN DESCRiPTIONS ....................................................................................... 1-12
CHAPTER 2
CACHE ARCHITECTURE OVERVIEW
2.1. MAIN FEATURES ......................................................................................................... 2-2
2.2. CPU/CACHE CORE DESCRIPTION ............................................................................ 2-2
2.2.1.
82496 Cache Controller ............................................................................................ 2-2
2.2.2. 82491 Cache SRAMs ............................................................................................... 2-3
2.2.3. Memory Bus Controller ............................................................................................. 2-4
2.3. CONFIGURATION ........................................ : ............................................................... 2-5
2.3.1. Physical Cache ......................................................................................................... 2-5
2.3.2. Snoop Modes ............................................................................................................ 2-6
2.3.2.1. SYNCHRONOUS SNOOP MODE ........................................................................ 2-6
2.3.2.2. CLOCKED (ASYNCHRONOUS) SNOOP MODE ................................................. 2-6
2.3.2.3. STROBED SNOOP MODE ................................................................................... 2-6
2.3.3. Memory Bus Modes .................................................................................................. 2-6
2.3.3.1. CLOCKED MEMORY BUS MODE ........................................................................ 2-7
2.3.3.2. STROBED MEMORY BUS MODE ........................................................................ 2-7
2.4. PENTIUM PROCESSOR BUS INTERFACE ................................................................ 2-7
2.5. 82496 CACHE CONTROLLER/82491 CACHE SRAM OPTIMIZED INTERFACE ........ 2-8
2.6. MEMORY BUS INTERFACE ........................................................................................ 2-8
2.6.1. Snooping Logic ......................................................................................................... 2-8
2.6.2. Cycle Control Logic ................................................................................................... 2-9
2.7. TEST ............................................................................................................................. 2-9
CHAPTER 3
COMPONENT OPERATION
3.1. WRITE-THROUGH CACHE DESiGNS ......................................................................... 3-1
3.2. WRITE-BACK CACHE DESIGNS ................................................................................. 3-1
3.3. 82496 CACHE CONTROLLER CACHE CONSISTENCY PROTOCOL. ....................... 3-1
3.4. MESI CACHE CONSISTENCY PROTOCOL MODEL .................................................. 3-2
3.5. BASIC MESI STATE TRANSiTIONS ............................................................................ 3-3
3.5.1. MESI State Changes Resulting From CPU Bus Operations ..................................... 3-5
3.5.1.1. READ HIT ............................................................................................................. 3-5
3.5.1.2. READ MISS .......................................................................................................... 3-5
3.5.1.3. WRITE HIT ............................................................................................................ 3-6
3.5.1 .4. WRITE MiSS ......................................................................................................... 3-6
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