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Intel 810A3 Design Manual

Intel 810A3 Design Manual

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Intel
810A3 Chipset Platform
Design Guide
July 2000
Order Number:
298186-002

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Summary of Contents for Intel 810A3

  • Page 1 ® Intel 810A3 Chipset Platform Design Guide July 2000 Order Number: 298186-002...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    Motherboard Frequency Select for SC242 Designs ........3-6 S.E.C.C. 2 Grounding Retention Mechanism (GRM)........3-7 3.9.1 Motherboard Interfaces..............3-7 Layout and Routing Guidelines..................4-1 General Recommendations ................4-1 Nominal Board Stackup ................4-1 Component Quadrant Layouts..............4-2 ® Intel 810A3 Chipset Component Placement ..........4-4 ® Intel 810A3 Chipset Design Guide...
  • Page 4 4.14 Processor PLL Filter Recommendation ............4-28 4.14.1 Processor PLL Filter Recommendation .........4-28 4.14.2 Topology ..................4-28 4.14.3 Filter Specification .................4-28 4.14.4 Recommendation for Intel Platforms..........4-30 4.14.5 Custom Solutions................4-31 4.15 RAMDAC/Display Interface ................4-32 4.15.1 Reference Resistor (Rset) Calculation...........4-33 4.15.2 RAMDAC Board Design Guidelines..........4-33 4.16...
  • Page 5 Clock Routing Guidelines................6-3 Capacitor Sites....................6-6 Clock Power Decoupling Guidelines.............6-6 System Design Considerations..................7-1 Power Delivery....................7-1 ® 7.1.1 Intel 810A3 Chipset Power Delivery ..........7-1 7.1.2 LED Indicator for S0-S5 States............7-5 Decoupling Guidelines ..................7-6 7.2.1 Decoupling................7-6 CORE 7.2.2 Phase Lock Loop (PLL) Decoupling ..........7-6 7.2.3...
  • Page 6 RTCRESET External Circuit for the ICH RTC ..........4-27 4-29 Filter Topology ....................4-28 4-30 Filter Specification ..................4-29 4-31 Using Discrete R..................4-30 4-32 No Discrete R .....................4-31 4-33 Core Reference Model................4-31 4-34 Schematic of RAMDAC Video Interface .............4-32 ® Intel 810A3 Chipset Design Guide...
  • Page 7 810A3 Chipset Clock Architecture ............6-2 Different Topologies for the Clock Routing Guidelines .........6-5 Example of Capacitor Placement Near Clock Input Receiver.......6-6 ® Intel 810A3 Chipset Power Delivery Architecture ........7-2 82810A3 GMCH Power Plane Decoupling ...........7-8 G3-S0 Transistion ..................7-9 S0-S3-S0 Transition..................7-10 S0-S5-S0 Transition..................7-11 Pullup Resistor Example................8-15...
  • Page 8 Intel 810A3 Chipset Power Map ..............7-3 ® Intel 810A3 Chipset Voltage Regulator Specifications .......7-4 Power Sequencing Timing Definitions ............7-12 AGTL+ Connectivity Checklist for 370-Pin Socket Processors.....8-2 CMOS Connectivity Checklist for 370-Pin Socket Processors .....8-3 TAP Checklist for a 370-Pin Socket Processor ...........8-3 Miscellaneous Checklist for 370-Pin Socket Processors ......8-4...
  • Page 9 AC’97 ......................9-2 TMDS Transmitters..................9-3 9-10 TV Encoders ....................9-3 9-11 Combo TMDS Transmitters/TV Encoders ............9-3 9-12 LVDS Transmitter ..................9-3 PCI Devices and Functions................A-1 PCI Devices and Registers ................A-1 PCI Devices and Interrupts ................A-2 ® Intel 810A3 Chipset Design Guide...
  • Page 10 Revision History Revision Description Date Initial Release April 2000 • Minor edits throughout for clarity July 2000 • Added Section 7.2.4, Ground Flood Plane ® Intel 810A3 Chipset Design Guide...

  • Page 11: Introduction

    Introduction...
  • Page 12 This page is intentionally left blank...

  • Page 13: About This Design Guide

    Intel Celeron™ processor 66 MHz Front Side Bus designs. ® ® Intel 810E Chipset Platform Design Guide, order number 290675, references the Intel ® ® III processor 100 MHz / 133 MHz Front Side 82810E chipset device for the Intel Pentium Bus designs.

  • Page 14: Terminology And Definitions

    Introduction • Chapter 9, “Third-Party Vendor Information”— This chapter includes information regarding ® various third-party vendors who provide products to support the Intel 810A3 chipset. • Appendix A, “PCI Devices/Functions/Registers/Interrupts”— This appendix lists the PCI ® devices and functions supported by the Intel 810A3 chipset.
  • Page 15 (depending on the power state of the system). Usually, a dual power rail is derived from a standby supply during suspend operation and derived from a core supply during full-power operation. Edge Finger The cartridge electrical contact that interfaces to the SC242 connector. ® Intel 810A3 Chipset Design Guide...
  • Page 16 The trace of a Printed Circuit Board (PCB) that completes an electrical connection between two or more components. Network Length The distance between extreme bus agents on the network and does not include the distance connecting the end bus agents to the termination resistors. ® Intel 810A3 Chipset Design Guide...
  • Page 17 The branch from the trunk terminating at the pad of an agent. Suspend operation During suspend operation, power is removed from some components on the motherboard. The customer reference board supports three suspend states: processor Stop Grant (S1), Suspend-to-RAM (S3) and Soft-off (S5). ® Intel 810A3 Chipset Design Guide...
  • Page 18 (STR) unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. Intel uses a 50 Ω test load for specifying its components. Test Load Trunk The main connection, excluding interconnect branches, terminating at agent pads.

  • Page 19: References

      The Intel 810A3 chipset is the first generation Integrated Graphics chipset designed for the Intel Celeron processor. The graphics accelerator architecture consists of dedicated multi-media engines executing in parallel to deliver high performance 3D, 2D, and motion compensation video capabilities.

  • Page 20: Graphics And Memory Controller Hub (Gmch)

    The Intel Celeron™ processor PPGA utilizes the AGTL+ system bus used by the ® Pentium II processor with support limited to single processor-based systems. The Intel Celeron™ processor PPGA includes an integrated 128 KB second level cache with separate 16K instruction and 16K data level one caches.

  • Page 21: I/O Controller Hub (82801Aa Ich)

    - Video Engine (ICH=6 Req/Gnt pairs) (4 MB SDRAM,100 MHz) PCI Bus Super Option 2 IDE Ports (I/O Controller Hub) Ultra ATA/66 Option AC'97 2 USB Audio Codec Ports Modem Codec FWH Flash BIOS ® Intel 810A3 Chipset Design Guide...

  • Page 22: Platform Initiatives

     The Intel 810A3 chipset platform integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.

  • Page 23: Ac'97

    By using a split design, the audio codec can be on-board and the modem codec can be placed on a riser. Intel is developing an AC’97 digital link connector. With a single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel where the external ports can be located.

  • Page 24: Low Pin Count (Lpc) Interface

     In the Intel 810A3 chipset platform, the Super I/O (SIO) component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components.

  • Page 25: Pga370 Processor Design Guidelines

    PGA370 Processor Design Guidelines...
  • Page 26 This page is intentionally left blank...

  • Page 27: Electrical Differences For Flexible Pga370 Designs

    Legacy PGA370 refers to today’s Intel 810A3 chipset platforms utilizing the PGA370 socket for the microprocessor. In general, these designs support 66/100 ® MHz host bus operation, VRM 8.2 DC-DC Converter Guidelines, and Intel Celeron processors. ® • Flexible PGA370 refers to new generation Intel 810A3/810E chipset platforms utilizing the PGA370 socket and designed for microprocessor flexibility.

  • Page 28: Pga370 Socket Definition Details

    Power Reserved BERR# Bus error AGTL+, I/O Reserved A34# Additional AGTL+ address AGTL+, I/O Processor reset (Value RESET# RESET2# AGTL+, I processors) Reserved A32# Additional AGTL+ address AGTL+, I/O CLKREF 1.25V PLL reference Power ® Intel 810A3 Chipset Design Guide...

  • Page 29: Processor Pin Definition Comparison

    1. These signals were previously defined as ground (Vss) connections in legacy designs utilizing the PGA370 socket to provide termination for unused inputs. For new Flexible PGA370 designs, use the new signal definitions. These new signal definitions are backwards compatible with the Intel® Celeron processor (PPGA).
  • Page 30 Pentium III processor must also be configured to 110 Ω internal Rtt.  Note: 133 MHz system bus frequency is not supported on the Intel 810A3 chipset. Initial Timing Analysis Table 2-3 lists the AGTL+ component timings of the processors and 82810A3 GMCH defined at the pins.

  • Page 31: Calculations For 100 Mhz Bus

    2. BCLK period = 10 ns @ 100 MHz. 3. The flight times in this column include margin to account for the following phenomena that Intel has observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and signal quality and are sometimes not accounted for in simulation.

  • Page 32: Topology For 370-Pin Socket Designs With Single Ended Termination (Set)

    Extra care is required in SET simulations to make sure that the  ringback specs are met under the worst case signal quality conditions. Intel 810A3 chipset designs require all AGTL+ signals to be terminated with a 56 Ω termination on the motherboard.
  • Page 33 This can create a large undershoot, followed by ringback which may violate the ringback specifications. This “wired-OR” situation should be simulated for the following signals: AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#. ® Intel 810A3 Chipset Design Guide...

  • Page 34: Routing For Thrmdp And Thrmdn

    1 -- Maximize (min - 20 mils) THRMDP 2 -- Minimize THERMDN 1 -- Maximize (min - 20 mils) Signal Z • Rule — Length Equalization route these traces parallel ±0.5” — Layer route both on the same layer ® Intel 810A3 Chipset Design Guide...

  • Page 35: Undershoot/Overshoot Requirements

    2.2.4 BSEL[1:0] Implementation for PGA370 Designs ® ® While the BSEL0 signal is still connected to the PGA370 socket, the Intel Pentium III processor  does not utilize it. Only the Intel Celeron...

  • Page 36: Clkref Circuit Implementation

    (2.1V) and a minimum absolute undershoot voltage limit (- ® ® 0.35V). Exceeding these limits will cause damage to the Intel Pentium III processor. There is also a time dependent, non-linear overshoot and undershoot requirement that is dependent on the ®...

  • Page 37: Connecting Reset# And Reset2# On A Flexible Pga370 Design

    C P U cs_rtt_stub CPU_rtt_stub   On legacy Intel 810A3 chipset platforms (ones that only have support for Intel Celeron™  processors), RESET# is delivered only to pin X4. On Flexible Intel 810A3 Chipset platforms ...

  • Page 38: Voltage Regulation Differences

    III (FC-PGA w/256K L2 cache) processor requires the VRM or on-board The Intel Pentium voltage regulator to be compliant with Intel VRM 8.4 DC-DC Converter Design Guidelines revision 1.5 or greater. Important points to note regarding VRM 8.4 are: ...

  • Page 39: Thermal/Emi Differences

    • Different thermal design verification for FC-PGA compared to PPGA packaged processors. ® ® ® III processors are specified using Tjunction versus Tcase (used with Intel Intel Pentium Celeron processors). • New heatsink for FC-PGA package which is not backwards compatible with PPGA processors.

  • Page 40: Debug Port Changes

    2.2.12 Debug Port Changes ® ® III processor, changes are Due to the lower voltage technology employed with the Intel Pentium required to support the debug port. Previously, the test access port (TAP) signals used 2.5V logic.  ® ®...

  • Page 41: Sc242 Processor Design Guidelines

    SC242 Processor Design Guidelines...
  • Page 42 This page is intentionally left blank...
  • Page 43 ® processor/Intel 810A3 Chipset system bus. Note that assumed values for clock skew and clock jitter were used. Clock skew and clock jitter values are dependent on the clock components and distribution method chosen for a particular design and must be budgeted into the initial timing equations as appropriate for each design.

  • Page 44: Calculations For 100 Mhz Bus

    2. BCLK period = 10 ns @ 100 MHz. 3. The flight times in this column include margin to account for the following phenomena that Intel has observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and signal quality and are sometimes not accounted for in simulation.

  • Page 45: Determine General Topology And Layout

    Table 3-5. Trace Width:Space Guidelines Crosstalk Type Trace Width:Space Ratios Intragroup AGTL+ signals (same group AGTL+) 5:10 or 6:12 Intergroup AGTL+ signals (different group AGTL+) 5:15 or 6:18 AGTL+ to non-AGTL+ 5:20 or 6:24 ® Intel 810A3 Chipset Design Guide...

  • Page 46: Minimizing Crosstalk

    1” to 9” PICD[1:0] 5 mils 10 mils 1” to 8” PREQ# 5 mils 10 mils 1” to 9” 5 mils 10 mils 1” to 9” STPCLK# 5 mils 10 mils 1” to 9” ® Intel 810A3 Chipset Design Guide...

  • Page 47: Thrmdp And Thrmdn

    V is generated locally on the processor. Be sure to include decoupling capacitors. Guidelines for V distribution and decoupling are contained in AP-  III Processor Power Distribution Guidelines (Order # 245085). 907: Pentium ® Intel 810A3 Chipset Design Guide...

  • Page 48: Motherboard Frequency Select For Sc242 Designs

    10 K Ω R E F CK810 S E L 1 S E L 0 10 K Ω 10 KΩ L M D 2 9 L M D 1 3 G M C H ® Intel 810A3 Chipset Design Guide...

  • Page 49: Grounding Retention Mechanism (Grm)

    SC242 Processor Design Guidelines S.E.C.C. 2 Grounding Retention Mechanism (GRM) Intel is enabling a new S.E.P.P. (Single Edge Processor Package) style retention mechanism which will provide a grounding path for the heatsink on processors in the S.E.C.C. 2 (Single Edge Contact Cartridge) package.

  • Page 50: Detailed Drawing Of Minimum Ground Pad Size And Location

    The required thickness of the pad is less than 0.001” (using 1/2 oz copper). ® Intel 810A3 Chipset Design Guide...

  • Page 51: Layout And Routing Guidelines

    Layout and Routing Guidelines...
  • Page 52 This page is intentionally left blank...

  • Page 53: General Recommendations

    Nominal Board Stackup ® The Intel 810A3 chipset platform requires a board stackup yielding a target impedance of 60 Ω ±15% with a 5 mil nominal trace width. Figure 4-1 presents an example stackup to achieve this.

  • Page 54: Component Quadrant Layouts

    Solder SIde Layer 4 (1/2 oz. cu) Component Quadrant Layouts Figure 4-2. GMCH Quadrant Layout (topview) System Pin A1 Memory Interface System Memory Display Cache GMCH Top View Digital System Bus Video System Bus CRT Display ® Intel 810A3 Chipset Design Guide...

  • Page 55: Ich 241-Ubga Quadrant Layout (Topview)

    Figure 4-3. ICH 241-uBGA Quadrant Layout (topview) Pin #1 Corner P C I Processor I C H Hub Interface 2 4 1 u B G A AC'97, S M B u s L P C I D E ® Intel 810A3 Chipset Design Guide...

  • Page 56: Intel 810A3 Chipset Component Placement

    Layout and Routing Guidelines  Intel 810A3 Chipset Component Placement The assumptions for component placement are: • uATX Form Factor • 4-Layer Motherboard • Single Sided Assembly Figure 4-4. uATX Placement Example for PGA370 Processors ® Intel 810A3 Chipset Design Guide...

  • Page 57: System Memory Layout Guidelines

    SMD[63:0], SDQM[7:0] SCAS#, SRAS#, SWE# SBS[1:0], SMAA[11:8, 3:0] NOTE: It is recommended to add 10 Ω series resistors to the MAA[7:4] and the MAB[7:4] lines as close as possible to GMCH for signal integrity. ® Intel 810A3 Chipset Design Guide...

  • Page 58: System Memory Routing Example

    Layout and Routing Guidelines 4.5.2 System Memory Routing Example Figure 4-6. System Memory Routing Example ® Intel 810A3 Chipset Design Guide...

  • Page 59: System Memory Connectivity

    D I M M _ C L K [ 7 : 4 ] S M B _ C L K S M B _ D A T A DIMM 0 and 1 Display Cache Interface Figure 4-8. Display Cache (Topology 1) 1 M x 1 6 ® Intel 810A3 Chipset Design Guide...

  • Page 60: Display Cache Solution Space

    Figure 4-10. Display Cache (Topology 3) 1Mx16 2 2 O h m s 1Mx16 Table 4-4. Display Cache Routing (Topology 3) Trace (units=mils) D (inches) E (inches) F (inches) Signal Topology Width Spacing Length TCLK 0.75 1.25 ® Intel 810A3 Chipset Design Guide...

  • Page 61: Hub Interface

    Figure 4-12. Hub Interface Signal Routing Example H L _ S T B H L _ S T B # I C H G M C H HL[10:0] 3 V 6 6 3V66 C K 8 1 0 E ® Intel 810A3 Chipset Design Guide...

  • Page 62: Data Signals

    The reference voltage generated by a single HREF divider should be bypassed to ground at each component with a 0.01 uF capacitor located close to the component HREF pin. If the reference voltage is generated locally, the bypass capacitor needs to be close to the component HREF pin. ® 4-10 Intel 810A3 Chipset Design Guide...

  • Page 63: Compensation

    Compensation There are two options for the ICH hub interface compensation (HLCOMP). HLCOMP is used by ® the ICH to adjust buffer characteristics to specific board characteristics. Refer to the Intel ® 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub Datasheet for details on compensation.

  • Page 64: Ultra Ata/66

    40 pin connectors do not change. The wires in the cable alternate: ground, signal, ground, signal, ground, signal, ground, etc. All the ground wires are tied together on the cable (and they are tied to ® 4-12 Intel 810A3 Chipset Design Guide...

  • Page 65: Ultra Ata/66 Cable

    PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification). — If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be grounded and the output signals left as no connects. ® Intel 810A3 Chipset Design Guide 4-13...

  • Page 66: Resistor Schematic For Primary Ide Connectors

    I R Q 1 5 S D D A C K # 4 7 0 o h m C S E L Pin32 N.C. I C H *Due to high loading, PCIRST# must be buffered. ® 4-14 Intel 810A3 Chipset Design Guide...

  • Page 67: Ultra Ata/66 Detection

    Ultra ATA/66 Motherboard Guidelines ® The Intel 810A3 chipset can use two methods to detect the cable type. Each mode requires a different motherboard layout. Host-Side Detection—BIOS Detects Cable Type Using GPIOs Host side detection requires the use of two GPI pins (1 per IDE controller). The proper way to...

  • Page 68: Host-Side Ide Cable Detection

    The drive can detect the difference in rise times and it reports the cable type to the BIOS when it sends the IDENTIFY_DEVICE packet during system boot as described in the ATA/66 specification. ® 4-16 Intel 810A3 Chipset Design Guide...

  • Page 69: Host-Side Ide Cable Detection

    — R2 is a 15 KΩ resistor — C1 is not stuffed • For Drive-Side Detection — R1 is not stuffed — R2 is not stuffed — C1 is a 0.047 uF capacitor Figure 4-21. Host-Side IDE Cable Detection ® Intel 810A3 Chipset Design Guide 4-17...

  • Page 70: Audio/Modem Riser Card (Amr)

    The ICH implements an AC’97 2.1 compliant digital controller. Any codec attached to the ICH AC-link should be AC’97 2.1 compliant as well. Contact your preferred codec vendor for information on AC’97 2.1 compliant products. The AC’97 2.1 specification is on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The ICH supports the following combinations of codecs: Table 4-6.

  • Page 71: Ac'97 Routing

    AC’97 interface: the tee topology and the daisy-chain topology. The AC’97 link signals can be routed using 5 mil traces with 5 mil space between the traces. NLX routing recommendations will be provided in a future revision of this document. ® Intel 810A3 Chipset Design Guide 4-19...

  • Page 72: Tee Topology Ac'97 Trace Length Requirements For Atx

    To provide wake capability and/or caller ID, standby power must be provided to the modem codec. If no codec is attached to the link, internal pulldowns will prevent the inputs from floating; therefore, external resistors are not required. ® 4-20 Intel 810A3 Chipset Design Guide...

  • Page 73: Motherboard Implementation

    The values used are design dependent and should be verified for correct timings. The ICH AC-link output buffers are designed to meet the AC'97 2.1 specification with the specified load of 5. ® Intel 810A3 Chipset Design Guide 4-21...

  • Page 74: Usb

    The P+/P- signal traces should also be the same length. This minimizes the effect of common mode current on EMI. • 47 pF capacitors should be placed as close as possible to the USB connectors to help minimize EMI radiation. ® 4-22 Intel 810A3 Chipset Design Guide...

  • Page 75: Ioapic (I/O Advanced Programmable Interrupt Controller)

    150 Ω resistor • Tie PICD0 to VCC CMOS through a 150 Ω resistor • Tie PICD1 to VCC CMOS Note: If not using IOAPIC, turn off APIC clocks to ICH through I ® Intel 810A3 Chipset Design Guide 4-23...

  • Page 76: Pci

    PCI REQ#/GNT# pair. The ICH, based on simulations done by Intel, it is recommended that four is the maximum number of PCI slots that should be connected to the ICH. This limit is due to timing and loading considerations established during simulations.

  • Page 77: External Capacitors

    (if used), and package. The following equation can be used to choose the external capacitance values (C2 and C3): Cload = (C2*C3)/(C2+C3) + Cparasitic C3 can be chosen such that C3 > C2; then, C2 can be trimmed to obtain the 32.768 KHz. ® Intel 810A3 Chipset Design Guide 4-25...

  • Page 78: Rtc Layout Considerations

    V C C 3 _ 3 S B Y VccRTC 1.0uF A standby power supply should be used to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy. ® 4-26 Intel 810A3 Chipset Design Guide...

  • Page 79: Rtc External Rtcreset Circuit

    • To minimize noise of VBIAS it is necessary to implement the routing guidelines described ® above and the required external RTC circuitry as described in the Intel 82801AA (ICH) and ® Intel 82801AB (ICH0) I/O Controller Hub Datasheet.

  • Page 80: Processor Pll Filter Recommendation

    < 0.5 dB attenuation in pass band (see DC drop in next set of requirements) > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency The filter specification is graphically shown in Figure 4-30. ® 4-28 Intel 810A3 Chipset Design Guide...
  • Page 81 DC voltage drop from VCC to PLL1 should be < 60mV, which in practice implies series R < 2 Ω; also means pass band (from DC to 1Hz) attenuation < 0.5dB for VCC = 1.1V, and < 0.35dB for VCC = 1.5V. ® Intel 810A3 Chipset Design Guide 4-29...

  • Page 82: Recommendation For Intel Platforms

    Layout and Routing Guidelines 4.14.4 Recommendation for Intel Platforms The following tables are examples of components that meet Intel’s recommendations, when configured in the topology presented in Figure 4-29. Table 4-8. Inductor Part Number Value Rated I 0.56 Ω (1W max) TDK MLF2012A4R7KT 4.7 uH...

  • Page 83: Custom Solutions

    5. Sweep across component/parasitic tolerances. 6. To observe IR drop, use DC current of 30 mA and minimum VCC level. CORE For other modules (interposer, DMM, etc), adjust routing resistor if desired, but use minimum numbers. ® Intel 810A3 Chipset Design Guide 4-31...

  • Page 84: Ramdac/Display Interface

    R s e t 1 % R e f e r e n c e Current Resistor (metal film) G r o u n d P l a n e NOTE: Diodes D are clamping diodes and may not be necessary to populate. ® 4-32 Intel 810A3 Chipset Design Guide...

  • Page 85: Reference Resistor (Rset) Calculation

    VGA connector to maximize EMI filtering effectiveness. The LC filter components for the RAMDAC/PLL power plane, de-coupling capacitors, latch-up protection diodes, and the reference resistor are recommended to be placed in close proximity to the respective pins. ® Intel 810A3 Chipset Design Guide 4-33...

  • Page 86: Ramdac Component And Routing Guidelines

    - Match the RGB Routes - Make Spacing Between the RGB Toutes a Min. of 20 mils via Straight Down to the Ground Plane NOTE: Diodes D are clamping diodes and may not be necessary to populate. ® 4-34 Intel 810A3 Chipset Design Guide...

  • Page 87: Dpll Filter Design Guidelines

     The Intel 810A3 chipset contains sensitive phase-locked loop circuitry, the DPLL, that can cause excessive dot clock jitter. Excessive jitter on the dot clock may result in a “jittery” image. An LC filter network connected to the DPLL analog power supply is recommended to reduce dot clock jitter.

  • Page 88: Filter Specification

    This resistance acts as a damping resistance for the filter and affects the filter characteristics. This resistance includes the routing resistance from the board power plane connection to the filter inductor, the filter inductor parasitic resistance, the routing ® 4-36 Intel 810A3 Chipset Design Guide...

  • Page 89: Recommended Routing/Component Placement

    DPLL VCCDA ball is less than 3.3 Ω to meet the IR drop requirement. ® Intel 810A3 Chipset Design Guide 4-37...

  • Page 90: Frequency Response (See Table 4-13)

    Figure 4-38. Figure 4-38. Frequency Response (see Table 4-13) Magnitude Response (VCCA) Curve 3 Curve 2 Curve 0 Curve 1 0.01 0.100E-3 0.100E-05 1 0 0 M H z ® 4-38 Intel 810A3 Chipset Design Guide...

  • Page 91: Resistance Values For Frequency Response Curves (See Figure 4-38)

    As series resistance (R ) increases, the filter response (i.e., attenuation TRACE DISCRETE in PLL bandwidth) improves. There is a limit of 3.3 Ω total series resistance of the filter to limit DC voltage drop. ® Intel 810A3 Chipset Design Guide 4-39...
  • Page 92 Layout and Routing Guidelines This page is intentionally left blank. ® 4-40 Intel 810A3 Chipset Design Guide...
  • Page 93 Advanced System Bus...
  • Page 94 This page is intentionally left blank...

  • Page 95: Advanced System Bus Design

    GMCH load. Systems using custom chipsets will require timing analysis and analog simulations specific to those components. The guideline recommended in this section is based on experience developed at Intel while ® Pro processor family and Intel Pentium III processor- developing many different Intel Pentium based systems.

  • Page 96: Initial Timing Analysis

    Equation 5-3. Maximum Flight Time ≤ Clock Period - T - CLK - CLK FLT_MAX CO_MAX SU_MIN SKEW JITTER Equation 5-4. Minimum Flight Time ≥ T + CLK FLT_MIN HOLD SKEW CO_MIN ® Intel 810A3 Chipset Design Guide...

  • Page 97: Determine General Topology, Layout, And Routing Desired

    Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis. However, simulation results at the device pins may be used later to correlate simulation performance against actual system measurements.
  • Page 98 Positioning drivers with faster edges closer to the middle of the network typically results in more noise than positioning them towards the ends. However, Intel has shown that drivers located in all positions (given appropriate variations in the other network parameters) can generate the worst- case noise margin.

  • Page 99: Place And Route Board

    Advanced System Bus Design Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s Z0 and S0. Intel therefore recommends that PCB parameters are controlled as tightly as possible, with ® ® III processor nominal a sampling of the allowable Z0 and S0 simulated.

  • Page 100: Trace Width Space Guidelines

    This document addresses AGTL+ layout for both 1 and 2-way 133 MHz/100 MHz processor/ ® Intel 810A3 chipset systems. Power distribution and chassis requirements for cooling, connector location, memory location, etc., may constrain the system topology and component placement location; therefore, constraining the board routing. These issues are not directly addressed in this document.

  • Page 101: Post-Layout Simulation

    Intel specifies signal integrity at the device pads and therefore recommends running simulations at the device pads for signal quality. However, Intel specifies core timings at the device pins, so simulation results at the device pins should be used later to correlate simulation performance against actual system measurements.

  • Page 102: Validation

    AGTL+ bus in a DP mode is closer to 25 Ω, AC loading is approximately 29 Ω since the driver effectively “sees” a 56 Ω termination resistor in parallel with a 60 Ω transmission line on the cartridge. ® Intel 810A3 Chipset Design Guide...

  • Page 103: Test Load Vs. Actual System Load

    , starting from the beginning of the driver transition at the pad. T must be generated using the same test load for T . Intel provides this timing value in the AGTL+ I/O buffer models. In this manner, the following valid delay equation is satisfied: Equation 5-5.

  • Page 104: Theory

    — The board loading impact on the effective T in the system. • The amount of skew and jitter in the system clock generation and distribution. • Changes in flight time due to cross-talk, noise, and other effects. ® 5-10 Intel 810A3 Chipset Design Guide...

  • Page 105: Cross-Talk Theory

    Signal propagates in both directions on aggressor line. Aggressor Figure 5-4. Transmission Line Geometry: (A) Microstrip (B) Stripline Signal Lines Signal Lines Dielectric, ε Dielectric, ε AC Ground Plane A. Microstrip B. Stripline ® Intel 810A3 Chipset Design Guide 5-11...
  • Page 106 13 to 19 resistors (for 14- and 20-pin components). These packages generally have too much inductance to maintain the voltage/current needed at each resistive load. Intel recommends using discrete resistors, resistor networks with separate power/ground pins for each resistor, or working with a resistor network vendor to obtain resistor networks that have acceptable characteristics.

  • Page 107: More Details And Insight

    1017 0 475 0 67 MICROSTRIP (ns/ft) Equation 5-9. Effective Propagation Speed ∗ (ns/ft) Equation 5-10. Effective Impedance Ω Equation 5-11. Distributed Trace Capacitance (pF/ft) Equation 5-12. Distributed Trace Inductance ∗ ∗ (nH/ft) ® Intel 810A3 Chipset Design Guide 5-13...

  • Page 108: Effective Impedance And Tolerance/Variation

    This method has the disadvantage of reducing area that can be used to route traces. These partial planes may also ® 5-14 Intel 810A3 Chipset Design Guide...

  • Page 109: One Signal Layer And One Reference Plane

    Figure 5-6. Layer Switch with One Reference Plane Signal Layer A Ground Plane Signal Layer B Figure 5-7. Layer Switch with Multiple Reference Planes (same type) Signal Layer A Ground Plane Layer Layer Ground Plane Signal Layer B ® Intel 810A3 Chipset Design Guide 5-15...

  • Page 110: Layer Switch With Multiple Reference Planes

    A signal that transitions from a stripline or microstrip through vias or pins to a component (GMCH, etc.) should have close proximity decoupling across all involved reference planes to ground for the device. ® 5-16 Intel 810A3 Chipset Design Guide...

  • Page 111: Clock Routing

    5.3.3.4 SC242 Connector Intel studies indicate that the use of thermal reliefs on the connector pin layout pattern (especially ground pins) should be minimized. Such reliefs (cartwheels or wagon-wheels) increase the net ground inductance and reduce the integrity of the ground plane to which many signals are referenced.

  • Page 112: Definitions Of Flight Time Measurements/Corrections And Signal Quality

    1.3 V (1.1 V + 200 mV) for rising edge ringback • 0.69 V (0.89 V – 200 mV) for falling edge ringback ® A violation of these ringback limits requires flight time correction as documented in the Intel Pentium II Processor Developer’s Manual. ®...

  • Page 113: Vref Guardband

    Intel recommends planning a layout schedule that allows time for each of the tasks outlined in this document.
  • Page 114 Advanced System Bus Design This page is intentionally left blank. ® 5-20 Intel 810A3 Chipset Design Guide...

  • Page 115: Clocking

    Clocking...
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  • Page 117: Clock Generation

    Clocking Clock Generation  There is only one clock generator component required in an Intel 810A3 chipset system. The CK810 is a mixed voltage component. Some of the output clocks are 3.3V and some of the output clocks are 2.5V. As a result, the CK810 device requires both 3.3V and 2.5V. These power supplies should be as clean as possible.

  • Page 118: Clock Architecture

    Clocking Clock Architecture  Figure 6-1. Intel 810A3 Chipset Clock Architecture Processor CPU_2_ITP APIC_0 2.5V CPU_1 CPU_0 Clock Synthesizer P W R D W N SEL1 SEL0 S D A T A Data SCLK Main Memory 2 DIMMS Address S D R A M 0...

  • Page 119: Clock Routing Guidelines

    33 Ω ± 5% APIC 10 Ω ± 5% Table 6-4 shows the layout dimensions for the clock routing. Note: All the clock signals must be routed on the same layer which reference to a ground plane. ® Intel 810A3 Chipset Design Guide...

  • Page 120: Layout Dimensions

    DIMM slots is important. Future board designs should attempt to route the DCLKREF trace so that the trace is not parallel to the DIMM slots or does not pass underneath the DIMM slots. This prevents noise coupling of memory-related signals into the 48 MHz clock signal. ® Intel 810A3 Chipset Design Guide...

  • Page 121: Different Topologies For The Clock Routing Guidelines

    Figure 6-2. Different Topologies for the Clock Routing Guidelines Layout 1 Layout 2 Layout 3 Socket/ Connector Layout 4 Socket/ Connector Layout 5 Layout 6 ® Intel 810A3 Chipset Design Guide...

  • Page 122: Capacitor Sites

    Clocking Capacitor Sites Intel recommends 0603 package capacitor sites placed as close as possible to the clock input receivers for AC tuning for the following signal groups: • GMCH • Processor • SDRAM/DCLK • 3V66 • 3V66 to the ICH0/ICH Figure 6-3.

  • Page 123: System Design Considerations

    System Design Considerations...
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  • Page 125: Power Delivery

    During STR, only the necessary devices are powered. These devices include: main memory, the  ICH resume well, PCI wake devices (via 3.3Vaux), the Intel 82559 LAN down chip, AC’97 and optionally USB (USB can only be powered if sufficient standby power is available). To ensure that enough power is available during STR, a thorough power budget should be completed.

  • Page 126: Intel ® 810A3 Chipset Power Delivery Architecture

    System Design Considerations  Figure 7-1. Intel 810A3 Chipset Power Delivery Architecture F A N ® Intel 810A3 Chipset Processor Platform Power Map Serial Ports Core: VCC_VID: 1.65V 17.2A S0, S1 ATX P/S V R M Core: VCC_VID: 2.0V Serial Xceivers-12: 12V ±1.2V Core: VCC_VID: 2.0V...

  • Page 127: Intel 810A3 Chipset Power Map

    System Design Considerations  Table 7-1. Intel 810A3 Chipset Power Map Voltage Voltage Voltage Current Power Current Power Voltage Description Max (SB) (SB) (mA) (mW) (mA) (mW) 1.5 V Processor V 1.365 1.635 2700 4414.5 1.8 V ICH Hub interface I/O 1.710...

  • Page 128: Intel 810A3 Chipset Voltage Regulator Specifications

    System Design Considerations  In addition to the power planes provided by the ATX power supply, an instantly available Intel 810A3 chipset system (using Suspend-to-RAM) requires additional power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to ...

  • Page 129: Led Indicator For S0-S5 States

    7.1.2 LED Indicator for S0-S5 States Although not required by the ACPI Specification, Intel recommends that an on-board LED be implemented that informs the user that the system is in a full-on or a sleep state (as opposed to a mechanical off state).

  • Page 130: Decoupling Guidelines

    Adequate decoupling capacitance should be placed near the power pins of the Intel Celeron™ processor PPGA. In order to obtain optimal performance Intel recommends using 10 or more 4.7 uF 1206-style capacitors and 19 or more 1.0 uF 0805-style capacitors when using a conventional Voltage Regulator Module.

  • Page 131: 82810A3 Gmch Decoupling Guidelines

    100 MHz or 133 MHz SDRAM interfaces are used. Power Plane Layout • Make the power planes as square as possible with no sharp corners. • Avoid crossing traces over multiple power planes. ® Intel 810A3 Chipset Design Guide...

  • Page 132: Ground Flood Planes

    It is based on extrapolations in both hardware and software technology over the life of the product. It does not represent the expected power generated by a power virus. The TDP of the GMCH component is 4.0 W. ® Intel 810A3 Chipset Design Guide...

  • Page 133: Power Sequencing

    Vcc3.3sus RSMRST# SLP_S3# SLP_S5# SUS_STAT# Vcc3.3core CPUSLP# PWROK Clocks Clocks invalid Clocks valid PCIRST# Cycle 1 from GMCH Cycle 1 from ICH Cycle 2 from GMCH Cycle 2 from ICH STPCLK# Freq straps CPURST# ® Intel 810A3 Chipset Design Guide...

  • Page 134: S0-S3-S0 Transition

    PCIRST# Cycle 1 from GMCH Cycle 1 from ICH Cycle 2 from GMCH Cycle 2 from ICH CPURST# SLP_S3# SLP_S5# PWROK Vcc3.3core Clocks Clocks valid Clocks invalid Clocks valid Freq straps Wake Event ® 7-10 Intel 810A3 Chipset Design Guide...

  • Page 135: S0-S5-S0 Transition

    PCIRST# Cycle 1 from GMCH Cycle 1 from ICH Cycle 2 from GMCH Cycle 2 from ICH CPURST# SLP_S3# SLP_S5# PWROK Vcc3.3core Clocks Clocks valid Clocks invalid Clocks valid Freq straps Wake Event ® Intel 810A3 Chipset Design Guide 7-11...

  • Page 136: Power Sequencing Timing Definitions

    Wake event to SLP_S3# inactive RTC clocks PCIRST# inactive to STPCLK# inactive PCI clocks SLP_S3# active to SLP_S5# active RTC clocks SLP_S5# inactive to SLP_S3# inactive RTC clocks NOTE: * This value is board dependent. ® 7-12 Intel 810A3 Chipset Design Guide...

  • Page 137: Design Checklist

    Design Checklist...
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  • Page 139: Design Review Checklist

    The following tables provide design considerations for the various portions of a design. Each table describes one of those portions, and is titled accordingly. Contact your Intel Field Representative for questions or issues regarding interpretation of the information contained in these tables.

  • Page 140: Agtl+ Connectivity Checklist For 370-Pin Socket Processors

    Connect to GMCH. NOTES: ® 1. For Intel Celeron™ (PPGA package) processor electrical compatibility, the motherboard must include ® AGTL+ termination resistors. If the Intel Celeron™ processor is not supported, AGTL+ termination is ® ® provided by the Intel Pentium III processor (except RESET#).

  • Page 141: Cmos Connectivity Checklist For 370-Pin Socket Processors

    PRDY# NOTES: 1. The ITP connector is different than the one previously specified for other Intel IA-32 processors. It is the female counterpart to the previously specified connector and is specifically for use with processors utilizing 1.5V CMOS TAP I/O signals.

  • Page 142: Miscellaneous Checklist For 370-Pin Socket Processors

    Connect to Vref voltage divider made up of 75 and 150 ohm 1% resistors connected to Vtt. VREF[7:0] Decoupling Guidelines: 4 ea. (min) 0.1 uF in 0603 package placed within 500 mils of VREF pins. ® Intel 810A3 Chipset Design Guide...

  • Page 143: Agtl+ Connectivity Checklist For Sc242 Processors

    Leave as No Connect (not supported by chipset). RS[2:0]# Connect to GMCH. RSP# Leave as No Connect (not supported by chipset). TRDY# Connect to GMCH. NOTES: 1. For SET (Single-Ended Termination) designs, no motherboard Rtt is present for AGTL+ signals. ® Intel 810A3 Chipset Design Guide...

  • Page 144: Cmos Connectivity Checklist For Sc242 Processors

    220 Ω pullup resistor to 3.3V, connect to CK810 REF pin via 10 KΩ series BSEL1 resistor, connect to GMCH LMD13 pin via 10KΩ series resistor. Tie to ground. 0 Ω resistors are an option instead of direct connection to ground. EMI[5:1] ® Intel 810A3 Chipset Design Guide...

  • Page 145: Special Consideration Checklist

    Series resistor 22 Ω ± 5%. TCLK Series resistor 33 Ω ± 5%. OCLK/RCLK Series resistor 33 Ω ± 5%. 48MHz Series resistor 33 Ω ± 5%. APIC Series resistor 10 Ω ± 5%. ® Intel 810A3 Chipset Design Guide...

  • Page 146: Ich Checklist

    The value of the SMBus pullups should reflect the number of loads on the bus. For most implementations with 4–5 loads, 4.7 KΩ resistors are recommended. OEMs SMBDATA should conduct simulation to determine exact resistor value. ® Intel 810A3 Chipset Design Guide...

  • Page 147: Ich Checklist

    3.3V. Table 8-12. ICH Checklist Checklist Line Items Comments GPIO27/ALERTCLK Add a 10 KΩ pullup resistor to 3VSB (3 volt standby) on both of these signals. GPIO28/ALERTDATA ® Intel 810A3 Chipset Design Guide...

  • Page 148: Gmch Checklist

    Checklist Line Items Comments  Pin 147 Connect to Ground (since Intel 810A3 chipset does not support registered DIMMs). WP (Pin 81 on the Add a 4.7 KΩ pullup resistor to 3.3V. This is a recommendation to write-protect the DIMMs) DIMM’s EEPROM.

  • Page 149: Display Cache Checklist

    Need 5.6 KΩ (approximate) pull-down resistor to ground. Need 470 Ω (approximate) pull-down resistor to ground. CSEL Can use a 10 KΩ (approximate) pull-up resistor to 5V for HD LED IDEACTP#, IDEACTS# implementation. IOCS16# Leave as No Connect. ® Intel 810A3 Chipset Design Guide 8-11...

  • Page 150: Clock Generator Checklist

    Each REQ64# and ACK64# requires its own pull-up. IDSEL lines to PCI 100 Ω series resistor. connectors SBO# 5.6 KΩ pull-up resistor to VCC3_3 or VCC5. SDONE 3Vaux Optional to 3VSB, but required if PCI devices supporting wakeup events. ® 8-12 Intel 810A3 Chipset Design Guide...

  • Page 151: Usb / Keyboard / Mouse Checklist

    Codecs on the AMR card should implement the EAPD powerdown pin, per the AC’97 AUDIO_PWRDN 2.1 specification, to control the amplifier. MONO_PHONE Connect to onboard audio codec if supported. MONO_OUT/ Connect to SPKR output from ICH or MONO_OUT from onboard codec. PC_BEEP PRIMARY_DN# See discussion above. ® Intel 810A3 Chipset Design Guide 8-13...

  • Page 152: Power Delivery Checklist

    Voltage tolerance requirements are met See individual component specification for each voltage tolerance. Total power consumption in S3 must be less than the rated standby supply Adequate power must be supplied by power supply. current. ® 8-14 Intel 810A3 Chipset Design Guide...

  • Page 153: Pullup And Pulldown Resistor Values

    = -t / (C * In(1-(V MIN / Vcc MIN) ) ) Figure 8-1. Pullup Resistor Example V c c V c c M a x Leakage pull_res.vsd ® Intel 810A3 Chipset Design Guide 8-15...

  • Page 154: Rtc

    The PWROK signal to the chipset is a 3V signal. • The core well power valid to PWROK asserted at the chipset is a minimum of 1 msec. • PWROK to the chipset must be deasserted after RSMRST#. ® 8-16 Intel 810A3 Chipset Design Guide...

  • Page 155: Pwrgood And Pwrok Logic

    S3 state. System designers should insure that PWROK signal designs are glitch free. Intel has observed anomalies on ATX PWRGOOD signals that cause glitches on PWROK signals. Populating ®...

  • Page 156: Power Button Implementation

    — All lights except a power state light must be off. — The system must be inaudible: silent or stopped fan; drives are off. Note: Contact Microsoft* for the latest information concerning PC9x and Microsoft* Logo programs. ® 8-18 Intel 810A3 Chipset Design Guide...
  • Page 157 Third Party...
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  • Page 159: Third-Party Vendor Information

    Intel 810A3 chipset. The list of vendors can be used as a starting point for the designer. Intel does not endorse any one vendor, nor guarantee the availability or functionality of outside components. Contact the manufacturer for specific information regarding performance, availability, pricing and compatibility.

  • Page 160: Software Dvd

    Conexant (formerly Rockwell) Tom Eichenberg 949-221-4164 Spence Jackson 512-343-6636 SigmaTel Arron Lyman 512-343-6636 x11 Staccato Systems Bob Starr 650-853-7035 Tritech Microelectronics, Inc. Rod Maier 408-941-1360 Jose Villafuerte (US) 408-467-2300 Yamaha Kazunari Fukaya (Japan) (0539) 62-6081 ® Intel 810A3 Chipset Design Guide...

  • Page 161: Tmds Transmitters

    CH7009/ Chrontel Chi Tai Hong [cthong@chrontel.com] (408) 544-2150 CH7010 TFP6422/ Greg Davis Texas Instrument (214) 480-3662 TFP6424 [gdavis@ti.com] Table 9-12. LVDS Transmitter Vendors Component Contact Phone Jason Lu National 387R (408) 721-7540 Semiconductor [Jason.Lu@nsc.com] ® Intel 810A3 Chipset Design Guide...
  • Page 162 Third-Party Vendor Information This page is intentionally left blank. ® Intel 810A3 Chipset Design Guide...
  • Page 163 Devices/Functions/ Registers/Interrupts...
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  • Page 165: Pci Devices And Functions

    AC'97 Modem Controller 8086h 0x2416 Note 1 82810A3 GMCH System and Memory Controller 8086h 0x7124 Note 1 Internal Graphics Device 8086h 0x7125 Note 1 NOTES: 1. See Specification Update document for the particular product. ® Intel 810A3 Chipset Design Guide...

  • Page 166: Pci Devices/Functions/Registers/Interrupts

    82801AA AC'97 Audio Controller Interrupt 17 PIRQB# ® Intel 82801AA AC'97 Modem Controller Interrupt 17 PIRQB# Reserved 82810A3 GMCH ® Intel 82810A3 System and Memory Controller ® Intel 82810A3 Internal Graphics Device Interrupt 16 PIRQA# ® Intel 810A3 Chipset Design Guide...

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