82491 Cache Sram; Brief Pin Descriptions; Meoc; Mfrz - Intel 82496 CACHE CONTROLLER User Manual

PINOUTS
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ntel
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1.2.3. 82491 Cache SRAM
Table 1-3. 82491 Cache SRAM Pin Cross Reference by Pin Name
Address CPU Bus Data Control
AO 65 CDATAO 48 ADS# 63 MEOC# 23
A1 66 CDATA1 54 BE# 64 MFRZ# 24
A2
67
CDATA2 49 BlAST# 59 MOClK 27
A3 68 CDATA3 55 BlEC# 34 MSEl# 25
A4
69
CDATA4 46 BOFF#
36
MZBT# 21
A5 70 CDATA5 51 BRDY# 60 RESET 28
A6 71 CDATA6 52 BRDYC# 61 TCK 3
A7 73 CDATA7 57
BUS# 40
TDI 2
A8 75
Memory
ClK 30
TDO
84
A9 76
Bus Data
CRDY# 43 TMS 1
A10 77 MDATAO 18 HITM# 62 W/R# 58
A11 78 MDATA1 14 MAWEA# 41 WAY 45
A12 79 MDATA2 10 MBE# 32 WBA
38
A13 80 MDATA3 6 MBRDY# 22 WBTYP 37
A14
81
MDATA4 16
MClK 26 WBWE# 39
A15 82 MDATA5 12 MCYC# 42 WRARR# 44
MDATA6 8 MDOE# 20
MDATA7 4
NC VCC VSS
83 5 17 50 7 19 47
9
29
56
11 31
53
13 35 74 15 33 72
1.3. BRIEF PIN DESCRIPTIONS
This section provides brief descriptions of all signals of the Pentium processor CPU-Cache
Chip Set.
The # symbol at the end of a signal name indicates that the active, or asserted state occurs
when the signal is at a low voltage. When a # symbol is not present after the signal name, the
signal is active, or asserted at the high voltage level.
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