Intel 82496 CACHE CONTROLLER User Manual page 337

HARDWARE INTERFACE
5.2.2.142. WAY
WAY Way
Indicates the way in which the current cache cycle is located.
Output from 82496 Cache Controller (pin M16), Input to 82491 Cache SRAM (pin
45)
Synchronous to ClK
Signal Description
WAY is driven to the 82491 Cache SRAM from the 82496 Cache Controller to indicate the
way of the current cache cycle.
If
WAY is driven high, the cycle will access way one.
If
WAY
is driven low, the cycle will access way zero.
The 82491 Cache SRAM samples WAY with WRARR# for normal write cycles and read hits
which miss the MRU bit. The 82491 Cache SRAM samples WAY with MCYC# for read miss
cycles. The 82491 Cache SRAM samples WAY with WBWE# for write back cycles.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
WRARR#
For write cycles, WRARR# qualifies the WAY input to the 82491 Cache SRAM to
determine in which way the data will be written.
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