Warm Reset; Handling Of Large Caches I Larger Line Sizes - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.1.8.
Warm Reset
Wann reset enables the CPU portion of the Pentium processor CPU-Cache Chip Set cache core
to be reset without resetting the primary or secondary caches (or the Pentium processor
floating point unit).
To initialize the Pentium processor without affecting the first level caches, the MBC can assert
INIT to the CPU as per the Pentium™ Processor Data Book.
5.1.9.
NOTE
Refer to the Pentium™ Processor Data Book for details on INIT. The 82496
Cache Controller/82491 Cache SRAM cache may be active while the
Pentium processor cache is being initialized. This is permitted because the
Pentium processor allows back-invalidations during initialization.
Handling of Large Caches / Larger Line Sizes
A 512K cache can be configured with either 64 byte or 128 byte line size. For a 128-bit bus
configuration, the 64 byte line size requires 4 bus transactions per cache line, whereas the 128
byte line size requires 8 transactions per cache line. In a 512K cache configuration, each
BE[7:0]# output of the Pentium processor connects to the BE# input of two 82491 Cache
SRAM devices.
A 512K cache can be connected to a 64-bit memory bus using the existing configuration
options, as well as some external logic and control. For a clocked memory bus implementation,
a description of a 512K cache connection to a 64-bit memory bus follows. The 82491 Cache
MDOE# input is divided into two signals: MDOEL# and MDOEH#. Similarly, the 82491
Cache SRAM MBRDY# input is divided into MBRDYL# and MBRDYH#. The 16 82491
Cache SRAM devices are split into a "low" bank, which outputs/inputs the low 64-bits of data
ont%ff of the memory bus, and a "high" bank, which outputs/inputs the high 64-bits of data
ont%ff of the memory bus. The MDOEL# and MBRDYL# signals are connected from the
MBC to the low bank; the MDOEH# and MBRDYH# signals are connected from the MBC to
the high bank. The MBC is responsible for asserting MDOEL#, MDOEH#, MBRDYL#, and
MBRDYH# such that no bus conflict occurs. The MDOEL# and MDOEH# signals retain the
same functionality and timing requirements as the MDOE# signal; however, the MDOEL#
signal, for example, only acts as the output enable for the low bank of 82491 Cache SRAM
devices. Similarly, the MBRDYL# and MBRDYH# signals retain the same functionality as
the MBRDY# signal. Refer to Figure 5-22 for a depiction of the 512K cache to 64-bit memory
bus connection.
During linefills to both the 82496 Cache Controller/82491 Cache SRAM and the Pentium
processor, the processor reads one half of a CPU cache line for each assertion of MBRDY#.
The MBC may start to assert BRDY# (for CPU data transfer) after it asserts the second
MBRDY# of memory bus transfer.
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