Apic - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.9.
APIC#
APIC# Advanced Programmable Interrupt Controller Address Decoding
Indicates cycle address in an APIC· address.
Output from 82496 Cache Controller (pin N01)
Synchronous to ClK
Refer to the "82489DX Advanced Programmable Interrupt Controller - Advance Information," July 1992,
Order Number 290446-001.
Signal Description
APIC# is asserted by the 82496 Cache Controller to indicate that the address of a given
memory cycle is an APIC address (i.e., FE EO 00 00 - FE EO 03 FF Hex). APIC is the
advanced programmable interrupt controller for 32 bit high performance operating systems.
It
has features built-in which improve performance in multitasking operating systems (both
uniprocessor and multiprocessor). It meets the functional requirements of interrupt controllers
in multiprocessor systems. Note that BT[3:0] must be low in order to ensure the proper
assertion of APIC#.
When Driven
APIC# is valid with CADS# and remains valid until CNA# or CRDY# is asserted.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CADS# Address and cycle specification signals (i.e., APIC#, CCACHE#,
CD/C#,
CM/IO#,
CPCD, CPWT, CSCYC,
CW/R#,
CWAY, KlOCK#, MAP, MBT[3:0), MCACHE#,
MCFA, MSET, MTAG, NENE#, PAllC#, RDYSRC, and SMlN#) are valid with
CADS#.
MCFA, MSET, MTAG APIC# is a pure address decode of MCFA, MSET, MTAG.
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