Intel 82496 CACHE CONTROLLER User Manual page 283

HARDWARE INTERFACE
5.2.2.98. MOSTB
MOSTS Memory Sus Output Strobe
Strobes data from the 82496 Cache Controller/82491 Cache SRAM.
Input to 82491 Cache SRAM (pin 27)
Asynchronous
Signal Description
MOSTB is an input to the 82491 Cache SRAM that cause the 82491 Cache SRAM to output
data through its memory data bus outputs on rising and falling edges. MOSTB is used with
MSEL# active to advance the memory burst address counter of the memory buffer in use. As a
result, new data is driven from the 82491 Cache SRAM memory cycle or write back buffers.
MOSTB is used only in strobed memory bus mode. In clocked memory bus mode, MOSTB is
the MOCLK input.
When Sampled
MOSTB is always sampled by the 82491 Cache SRAM. MOSTB must meet strobed mode
active and inactive times.
Relation to Other Signals
Pin Symbol Relation to Other Signals
MOCLK MOSTS shares a pin with MOCLK.
MSEL# MOSTS is qualified by the MSEL# input. When MSEL# is active, MOSTS
advances the memory burst counter for the memory buffer in use to output data
through the memory data bus pins.
MSTSM MSTSM determines whether the 82491 Cache SRAM operates in the strobed
memory bus mode or in clocked memory bus mode.
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