Mclk - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.87. MCLK
MCLK Memory Bus Clock
Memory bus Clock signal.
Input to 82491 Cache SRAM (pin 26)
Internal Pull-up
Signal Description
In clocked memory bus mode, MCLK provides the memory bus clock. 82491 Cache SRAM
Memory bus signals and memory bus data are sampled on the rising edge of MCLK. Memory
bus write data is driven with respect to MCLK or MOCLK depending upon the configuration.
MCLK need not have any relation to CLK. MCLK has minimum and maximum frequencies,
the maximum being the same as CLK (i.e., MCLK <= CLK).
Relation to Other Signals
Pin Symbol Relation to Other Signals
MBRDY#, In clocked memory bus mode, the memory bus, MSEL#, MFRZ#, MBRDY#,
MDATA[7:0], MFRZ#, MZBT# and MEOC# pins are sampled synchronously with the rising edge of
MOEC#, MSEL#, MCLK. In a clocked memory bus write, the memory bus outputs are driven
MZBT#
synchronously with MCLK or MOCLK.
MOCLK MOCLK is a delayed version of MCLK. MOCLK is provided to allow the system
designer to increase the minimum data hold time available to the memory bus
relative to MCLK when data is output from the 82491 Cache SRAM.
MSTBM MCLK shares a pin with MSTBM. Note that the MCLK/MSTBM pin only becomes
MGLK after the following condition: MCLK/MSTBM is toggled AFTER the third
CLK which occurs after RESET. Refer to the MSTBM pin description for more
details.
I
5-143