Intel 82496 CACHE CONTROLLER User Manual page 329

HARDWARE INTERFACE
5.2.2.135. SYNC#
SYNC# Synchronize
Synchronizes the cache array with main memory.
Input to 82496 Cache Controller (pin R05)
Asynchronous
Internal Pull-up
Signal Description
This signal causes the 82496 Cache Controller to write all modified second-level cache lines to
main memory in order to synchronize them. At the end of the synchronize operation, the
82496 Cache Controller tag array is not invalidated. All shared [S] and exclusive [E) entries
remain the same state, and modified [M] lines become unmodified [E) state lines and the lines
are written back to main memory.
All 82496 Cache Controller modified lines cause an inquire cycle to the Pentium processor to
determine if the Pentium processor contains more recently modified data. If so, the data from
the CPU is written back to the 82491 Cache SRAM write back buffers and, sometimes, to the
82491 Cache SRAM cache array. The data from the 82491 Cache SRAMs is then written back
to main memory.
To initiate a synchronize operation, the 82496 Cache Controller completes all pending cycles
and prevents further assertions of ADS# while the synchronize operation is in progress. The
FSIOUT# output signal indicates the start and end of the SYNC# operation. FSIOUT#
becomes active when SYNC# is internally recognized (when all outstanding cycles have
completed) and is de-activated when the synchronize operation has completed.
The 82496 Cache Controller can be snooped during SYNC# cycles, and the snooping
protocols will be the same as with any memory bus cycle.
When Sampled
SYNC# can be asserted at any time. The 82496 Cache Controller completes all outstanding
cycles on the CPU and memory bus before beginning the synchronize process. The memory
bus controller does not have to prevent SYNC# during locked cycles because the 82496 Cache
Controller completes the locked cycle before the synchronize operation begins.
Once a synchronize operation has begun, SYNC# is ignored until the operation completes. If
RESET or FLUSH# is asserted while the synchronize operation is in progress, the operation is
aborted and a reset or flush is executed immediately.
SYNC# is an asynchronous input. SYNC# must have a pulse width of two CLKs in order to
ensure 82496 Cache Controller recognition.
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