Intel 82496 CACHE CONTROLLER User Manual page 353

MEMORY BUS FUNCTIONAL DESCRIPTION
to the lines to be replaced. The 82491 Cache SRAM will actually perform the reading from the
ARRAY one clock after WBWE# is driven by the 82496 Cache Controller (which will be
drive around clocks 5 or 6). WBTYP will be driven low to the 82491 Cache SRAM to indicate
a write-back due to a replacement (WBTYP high indicates a write-back due to a snoop).
MKEN# is sampled active during KWEND# (clock 6), confirming the cacheability of the read
cycle. Since the line being replaced is Modified, an inquire cycle starts. (waiting until the
cacheability of the cycle is confirmed is necessary in order to avoid unneeded invalidations,
i.e. if the cycle turns out to be non-cacheable).
In clock 6, the line is inquired (the 82496 Cache Controller drives EADS# with active INV
since it is a replacement case). In clock 8, HITM# is sampled active, indicating the line has
been modified in the CPU.
After the snoop window closes, the MBC starts serving the CPU read cycle, which is
completed in clock 11 (see BLAST#.BRDY#). In clock 13 the CPU starts flushing back the
contents of the inquired line (WBTYP will be valid during the write back ADS# in order to
inform the 82491 Cache SRAM where to load the inquired data: replacement write-back or
snoop write-back buffer). The CPU data overwrites the corresponding 82491 Cache SRAM
write-back buffer. With the BLAST#.BRDYC# (clock 17) of the CPU write-back cycle, the
82496 Cache Controller activates CDTS# meaning that all data is available in the 82491 Cache
SRAM write-back buffer. AHOLD is deactivated (clock 18) one clock after
BLAST#.BRDYC# of the CPU write-back cycle.
On the memory bus, the 82496 Cache Controller issues a write-back (WB) cycle. CNA# is
sampled active in clock 5 causing the 82496 Cache Controller to issue the CADS# of the write-
back (clock 7). Note that CDTS# is issued later after completing the CPU write-back cycle
(clock 17). CNA# of a cycle can be activated only with or after CDTS# of that cycle. In this
example, CNA# is activated together with CDTS#.
Following the completion of the write back cycle on the CPU bus (BLAST#.BRDYCl# in
clock 17), a new read cycle (B) is issued in clock 19 with ADS#.
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