Intel 82496 CACHE CONTROLLER User Manual page 326

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol Relation to Other Signals
MAOE# If MAOE# is active when SNPSTB# is asserted, the snoop request is ignored.
MAP, MCFA, MSET, SNPSTB# latches the 82496 Cache Controller address (MSET, MTAG, MCFA)
MTAG and address parity (MAP) which is to be snooped.
MBAOE# SNPSTB# latches MBAOE#, using MAOE# as a qualifier.
If
MBAOE# is active when SNPSTB# is asserted, the 82496 Cache Controller
forces all bits in the sub-line address (the address bits controlled by MBAOE#) to
o
on a snoop write-back for a particular snoop and the snoop starts with sub-line
address
o.
SNPCYC# SNPSTB# must not be reasserted for a new snoop until after SNPCYC# is
asserted for a previous snoop.
SNPINV SNPSTB# latches SNPINV, using MAOE# as a qualifier. SNPINV and SNPNCA
provide the 82496 Cache Controller with snoop attributes affecting the state of a
snoop hit cache entry.
SNPNCA SNPSTB# latches SNPNCA, using MAOE# as a qualifier. SNPINV and SNPNCA
provide the 82496 Cache Controller with snoop attributes affecting the state of a
snoop hit cache entry.
SWEND# Snoops and memory accesses are interlocked. Once the 82496 Cache Controller
is granted the bus (when BGT# is asserted), it is capable of latching snoop
information with SNPSTB#, but does not execute the snoop (assert SNPCYC#)
until after the snoop window closes (when SWEND# is asserted).
I
5-201