Write Once Policy; Mesi State Tables (Pentium Processor Cpu-Cache Chip Set State Changes) - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
the 82496 Cache Controller will abort the CPU cycle by asserting BOFF# and will complete
the snoop or replacement first.
When FLUSH# is asserted to the 82496 Cache Controller, the 82496 Cache Controller back-
invalidates the CPU cache. If, during back-invalidation of the CPU cache, a modified line is
hit, the Pentium processor issues a writeback cycle. When SYNC# is asserted to the 82496
Cache Controller, the 82496 Cache Controller inquires the Pentium processor cache on every
82496 Cache Controller cache hit to a modified line. Both flush and sync cycles can cause the
write back of a modified line from the Pentium processor cache and the 82496 Cache
Controller/82491 Cache SRAM.
3.8.3.
Write Once Policy
The 82496 Cache Controller uses the WB/WT# signal to force the Pentium processor into a
write-once mode. This signal is used to ensure that the 82496 Cache Controller will always be
aware of Pentium processor potentially modified lines. The 82496 Cache Controller will only
allow the Pentium processor to go into exclusive states if tht; 82496 Cache Controller itself is
making a transition from Exclusive to Modified states or is already in M (e.g. from a previous
cycle with DRCTM# asserted). This insures that for any Pentium processor exclusive line, the
82496 Cache Controller will be in a modified state. Whenever the 82496 Cache Controller is
required to write-back a modified line to memory, it will first check the Pentium processor by
executing an inquire cycle.
Read only lines are treated as valid and invalid only. Neither the 82496 Cache Controller nor
the Pentium processor will cache read only lines in an exclusive or modified state. Therefore, a
82496 Cache Controller/82491 Cache SRAM line in an M or E state cannot have it's read only
bit set.
3.8.4.
MESI State Tables (Pentium Processor CPU-Cache Chip
Set State Changes)
Table 3-1 shows the basic MESI state transitions which apply to both the Pentium processor
and the 82496 Cache Controller/82491 Cache SRAM. The following tables (3-8, 3-9, 3-10)
show the state changes of the Pentium processor and 82496 Cache Controller/82491 Cache
SRAM during Read, Write, and Snoop cycles (respectively). The tables show the current and
final cache line states of both the Pentium processor and 82496 Cache Controller/82491 Cache
SRAM. They show the values of specific signals between the CPU and secondary cache which
can affect the line state. CPU and Memory bus activities are also shown.
A signal marked as a don't care ('x') in the following tables indicates that the value of the signal
is not used in determining the cache line state. The column labeled 'READ ONLY in 82496
Cache Controller/82491 Cache SRAM' represents either a valid line in the [S] state with the
read only bit set or a memory bus access with MRO# returned active by the MBC.
The purpose of this section is to highlight Pentium processor state changes; therefore, all
possible 82496' Cache Controller state changes are not covered. For a detailed description of
82496 Cache Controller/82491 Cache SRAM line state changes, refer to Tables 3-2 to 3-7.
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